- Improvements in pmgen: slices, choices, define, generate
- Added "xilinx_srl" for Xilinx shift register extraction
- Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
+ - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
+ - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
+ - Added "xilinx_dsp" for Xilinx DSP packing
+ - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
+ - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
+ - "synth_ice40 -dsp" to infer DSP blocks
Yosys 0.8 .. Yosys 0.9
----------------------
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
- $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
+ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v))
+ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v))