re PR target/68917 (test suite failure for builtin-bitops-1.c)

	PR target/68917
	* config/tilegx/tilegx.md (clzsi2): Don't create DI subregs of
	SI values.  Explicitly convert SI to DI and vice-versa.

From-SVN: r232028

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7d27a83413055c85dbe3892139c03f1742ac6898..8b1fd2d3536e820eff592de78a50dc1f57777402 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-01-01  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+       PR target/68917
+       * config/tilegx/tilegx.md (clzsi2): Don't create DI subregs of
+       SI values.  Explicitly convert SI to DI and vice-versa.
+
 2016-01-01  Jakub Jelinek  <jakub@redhat.com>
 
        PR tree-optimization/69070

diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md
index 944953c34b2da0ef64bb72e4252f7a02cfae70c8..a2c1aef3975b9223b94639cbfe53710619dfaea0 100644 (file)
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -1799,13 +1799,16 @@
 
 (define_expand "clzsi2"
   [(set (match_dup 2)
-        (ashift:DI (match_operand:SI 1 "reg_or_0_operand" "")
+       (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" "")))
+   (set (match_dup 2)
+       (ashift:DI (match_dup 2)
                    (const_int 32)))
-   (set (subreg:DI (match_operand:SI 0 "register_operand" "") 0)
-       (clz:DI (match_dup 2)))]
+   (set (match_dup 2)
+       (clz:DI (match_dup 2)))
+   (set (match_operand:SI 0 "register_operand" "")
+       (subreg:SI (match_dup 2) 0))]
    ""
    {
-     operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);
      operands[2] = gen_reg_rtx (DImode);
    })