fhdl/specials/memory: do not write address register for async reads

diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index 842cb55e0fe0c12cacce34a699ad8b17657949db..59ef73038f0b110dd69a472adcf42d5834cf9e8d 100644 (file)
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -258,11 +258,11 @@ class Memory(Special):
                                        elif port.mode == NO_CHANGE:
                                                rd = "\tif (!" + gn(port.we) + ")\n" \
                                                  + "\t\t" + bassign
-                       if port.re is None:
-                               r += rd
-                       else:
-                               r += "\tif (" + gn(port.re) + ")\n"
-                               r += "\t" + rd.replace("\n\t", "\n\t\t")
+                               if port.re is None:
+                                       r += rd
+                               else:
+                                       r += "\tif (" + gn(port.re) + ")\n"
+                                       r += "\t" + rd.replace("\n\t", "\n\t\t")
                        r += "end\n\n"
                
                for port in memory.ports: