attempting to use PowerDecode2 in non-svp64 mode

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 275136e9c3642c4fe2d6405d3f8e69c247110ade..51dfd6fe74beaf86638509982a6555162f9fca08 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1298,7 +1298,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         remap_en = self.svstate.SVme
         persist = self.svstate.RMpst
         active = (persist or self.last_op_svshape) and remap_en != 0
-        yield self.dec2.remap_active.eq(remap_en if active else 0)
+        if self.is_svp64_mode:
+            yield self.dec2.remap_active.eq(remap_en if active else 0)
         yield Settle()
         if persist or self.last_op_svshape:
             remaps = self.get_remap_indices()
@@ -1345,7 +1346,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
         # after that, settle down (combinatorial) to let Vector reg numbers
         # work themselves out
         yield Settle()
-        remap_active = yield self.dec2.remap_active
+        if self.is_svp64_mode:
+            remap_active = yield self.dec2.remap_active
+        else:
+            remap_active = False
         log ("remap active", bin(remap_active))
 
         # main input registers (RT, RA ...)

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 4057271370071c2a0e3b803b596aaadc42f5db12..550d7eb21a38f0f5ac73a794dc05343e1900bd44 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -140,7 +140,7 @@ class TestRunnerBase(FHDLTestCase):
                              nocore=False,
                              xics=False,
                              gpio=False,
-                             regreduce=True,
+                             regreduce=not self.allow_overlap,
                              svp64=self.svp64,
                              allow_overlap=self.allow_overlap,
                              mmu=self.microwatt_mmu,