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diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index cdcddc61edf8f4f213e4f257c8b2045b8cba34a6..42a08c5a5272ad048a9d98c73c34fe278a3ac859 100644 (file)
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -204,7 +204,7 @@ detect*).
 SVP64 has the means to mark registers as scalar or vector. However
 the available space in the prefix is extremely limited (9 bits).
 With effectively 5 operands (3 in, 2 out) some compromises are needed.
-However a little though gives a useful workaround: two modes,
+A little though gives a useful workaround: two modes,
 controlled by a single bit in `RM.EXTRA`, determine whether the 5th
 register is set to RC or whether to RT+VL. This then leaves only
 4 registers to qualify as scalar/vector, and this can use four