fix tests

diff --git a/src/nmigen_gf/hdl/test/__init__.py b/src/nmigen_gf/hdl/test/__init__.py
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/src/nmigen_gf/hdl/test/test_clmul.py b/src/nmigen_gf/hdl/test/test_clmul.py
index ffff3f0edf7c68c91cf109ff3de5f5a440e8a78b..ed39fedf32a5b595997e44ea9dbb8fccd5898186 100644 (file)
--- a/src/nmigen_gf/hdl/test/test_clmul.py
+++ b/src/nmigen_gf/hdl/test/test_clmul.py
@@ -11,7 +11,7 @@ from nmigen.hdl.ast import (AnyConst, Assert, Signal, Const, unsigned, signed,
                             Mux)
 from nmigen.hdl.dsl import Module
 from nmutil.formaltest import FHDLTestCase
-from nmutil.openpower_sv_bitmanip_in_wiki.clmul import clmul
+from nmigen_gf.reference.clmul import clmul
 from nmutil.clmul import BitwiseXorReduce, CLMulAdd
 from nmigen.sim import Delay
 from nmutil.sim_util import do_sim, hash_256