back.verilog: remove $verilog_initial_trigger after proc_prune.

$verilog_initial_trigger was introduced to work around Verilog
simulation semantics issues with `always @*` statements that only
have constants on RHS and in conditions. Unfortunately, it breaks
Verilator. Since the combination of proc_prune and proc_clean passes
eliminates all such statements, it can be simply removed when both
of these passes are available, currently on Yosys master. After
Yosys 0.10 is released, we can get rid of $verilog_initial_trigger
entirely.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index accaeb0ed0da6aa0b2b7370515f0856a1a25cc59..5cd9f97fc914686db2d9d8ac54552d8ba84e808a 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -899,6 +899,14 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
                     # by looking for any signals on RHS. If there aren't any, we add some logic
                     # whose only purpose is to trigger Verilog simulators when it converts
                     # through RTLIL and to Verilog, by populating the sensitivity list.
+                    #
+                    # Unfortunately, while this workaround allows true (event-driven) Verilog
+                    # simulators to work properly, and is universally ignored by synthesizers,
+                    # Verilator rejects it.
+                    #
+                    # Running the Yosys proc_prune pass converts such pathological `always @*`
+                    # blocks to `assign` statements, so this workaround can be removed completely
+                    # once support for Yosys 0.9 is dropped.
                     if not stmt_compiler._has_rhs:
                         if verilog_trigger is None:
                             verilog_trigger = \

diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py
index 8faf58adb4c088bccfb0b4162cd711e3e54213b9..eb98a34cf1dd42fa88d70ad832d81646526430a2 100644 (file)
--- a/nmigen/back/verilog.py
+++ b/nmigen/back/verilog.py
@@ -39,6 +39,7 @@ def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog
 read_ilang <<rtlil
 {}
 rtlil
+{prune}delete w:$verilog_initial_trigger
 {prune}proc_prune
 proc_init
 proc_arst