``prove`` Unbounded model check to verify safety properties (``assert(...)`` statements)
``live`` Unbounded model check to verify liveness properties (``assert(s_eventually ...)`` statements)
``cover`` Generate set of shortest traces required to reach all cover() statements
+``equiv`` Formal equivalence checking (usually to verify pre- and post-synthesis equivalence)
+``synth`` Reactive Synthesis (synthesis of circuit from safety properties)
========= ===========
All other options have default values and thus are optional. The available
| | | consistency. Values: ``on``, ``off``. Default: ``off`` |
+-------------+------------+---------------------------------------------------------+
| ``aigsmt`` | All | Which SMT2 solver to use for converting AIGER witnesses |
-| | | to counter example traces. Default: ``yices`` |
+| | | to counter example traces. Use ``none`` to disable |
+| | | conversion of AIGER witnesses. Default: ``yices`` |
+-------------+------------+---------------------------------------------------------+
| ``smtc`` | ``bmc``, | Pass this ``.smtc`` file to the smtbmc engine. All |
| | ``prove``, | other engines are disabled when this option is used. |
job.terminate()
- if task_status == "FAIL":
+ if task_status == "FAIL" and job.opt_aigsmt != "none":
task2 = SbyTask(job, "engine_%d" % engine_idx, job.model("smt2"),
("cd %s; %s -s %s --noprogress --append %d --dump-vcd engine_%d/trace.vcd --dump-vlogtb engine_%d/trace_tb.v " +
"--dump-smtc engine_%d/trace.smtc --aig model/design_aiger.aim:engine_%d/trace.aiw --aig-noheader model/design_smt2.smt2") %
job.terminate()
- if task_status == "FAIL":
+ if task_status == "FAIL" and job.opt_aigsmt != "none":
if produced_cex:
if mode == "live":
task2 = SbyTask(job, "engine_%d" % engine_idx, job.model("smt2"),