synth_xilinx to techmap FFs after abc call, otherwise -retime fails

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 805ae8e6e93844d8e2c60340bd098c858b4c3e24..99c2be4200f99be49293c1bda8ad2ef7ee4844ae 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -256,9 +256,9 @@ struct SynthXilinxPass : public Pass
                        Pass::call(design, "opt -full");
 
                        if (vpr) {
-                               Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
+                               Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
                        } else {
-                               Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
+                               Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
                        }
 
                        Pass::call(design, "hierarchy -check");
@@ -269,7 +269,7 @@ struct SynthXilinxPass : public Pass
                {
                        Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
                        Pass::call(design, "clean");
-                       Pass::call(design, "techmap -map +/xilinx/lut_map.v");
+                       Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
                }
 
                if (check_label(active, run_from, run_to, "map_cells"))