[AArch64] Rename the internal "Upl" constraint

The SVE port uses the public constraints "Upl" and "Upa" to mean
"low predicate register" and "any predicate register" respectively.
"Upl" was already used as an internal-only constraint by the
addition patterns, so this patch renames it to "Uaa" ("two adds
needed").

2017-11-01  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/constraints.md (Upl): Rename to...
	(Uaa): ...this.
	* config/aarch64/aarch64.md
	(*zero_extend<SHORT:mode><GPI:mode>2_aarch64, *addsi3_aarch64_uxtw):
	Update accordingly.

Reviewed-By: James Greenhalgh  <james.greenhalgh@arm.com>
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r254326

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fc88c85a4a6cc101271836cf827ca6a53dec6213..98fc25ee90f4d3198600aff4de8585e2fa37fe0d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2017-11-01  Richard Sandiford  <richard.sandiford@linaro.org>
+           Alan Hayward  <alan.hayward@arm.com>
+           David Sherwood  <david.sherwood@arm.com>
+
+       * config/aarch64/constraints.md (Upl): Rename to...
+       (Uaa): ...this.
+       * config/aarch64/aarch64.md
+       (*zero_extend<SHORT:mode><GPI:mode>2_aarch64, *addsi3_aarch64_uxtw):
+       Update accordingly.
+
 2017-11-01  Richard Sandiford  <richard.sandiford@linaro.org>
            Alan Hayward  <alan.hayward@arm.com>
            David Sherwood  <david.sherwood@arm.com>

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index bbd5174df75ff0ddb5d2cf84aa7d4524f59fb858..ce75cf4171dde3d3b5dbf053f91d5e4da233e85e 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1562,7 +1562,7 @@
     (match_operand:GPI 0 "register_operand" "=rk,rk,w,rk,r")
     (plus:GPI
      (match_operand:GPI 1 "register_operand" "%rk,rk,w,rk,rk")
-     (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Upl")))]
+     (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Uaa")))]
   ""
   "@
   add\\t%<w>0, %<w>1, %2
@@ -1580,7 +1580,7 @@
     (match_operand:DI 0 "register_operand" "=rk,rk,rk,r")
     (zero_extend:DI
      (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk,rk")
-              (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Upl"))))]
+             (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Uaa"))))]
   ""
   "@
   add\\t%w0, %w1, %2

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index 77c510cea0d9da7cbce2e5d42823de6b288a153f..77ca85d929a36ca6ae407f933062e57a02b0b2f3 100644 (file)
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -35,7 +35,7 @@
  (and (match_code "const_int")
       (match_test "aarch64_uimm12_shift (ival)")))
 
-(define_constraint "Upl"
+(define_constraint "Uaa"
   "@internal A constant that matches two uses of add instructions."
   (and (match_code "const_int")
        (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))