iris: Use ISL_AUX_USAGE_HIZ_CCS_WT to indicate write-through HiZ

Previously, we always set the aux_usage to ISL_AUX_USAGE_HIZ_CCS and let
ISL choose write-through based on isl_surf_supports_hiz_ccs_wt.  This
commit makes us choose explicitly at surface creation time whether to
use HIZ_CCS or HIZ_CCS_WT based on the same set of conditions.  This is
more explicit and should be more robust as it lets us choose WT mode in
one place rather than trusting isl_surf_supports_hiz_ccs_wt to return
the same thing every time.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>

diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c
index 8dca0c4a3622665fb660c3633c9934ef78cbedb6..43382f9195485b62b71397dc974cfd7be5d1ccfc 100644 (file)
--- a/src/gallium/drivers/iris/iris_blit.c
+++ b/src/gallium/drivers/iris/iris_blit.c
@@ -577,6 +577,7 @@ get_copy_region_aux_settings(struct iris_context *ice,
    switch (res->aux.usage) {
    case ISL_AUX_USAGE_HIZ:
    case ISL_AUX_USAGE_HIZ_CCS:
+   case ISL_AUX_USAGE_HIZ_CCS_WT:
       if (is_render_target) {
          *out_aux_usage = res->aux.usage;
       } else {

diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c
index cfd7d53eb38ed955113a01999fc3043379f97b32..fdb45a37c71b1fe208cd2a6732f9e1fefe0d75c0 100644 (file)
--- a/src/gallium/drivers/iris/iris_resolve.c
+++ b/src/gallium/drivers/iris/iris_resolve.c
@@ -569,10 +569,9 @@ iris_sample_with_depth_aux(const struct gen_device_info *devinfo,
          break;
       return false;
    case ISL_AUX_USAGE_HIZ_CCS:
-      /* Write through mode must have been enabled for prior writes. */
-      if (isl_surf_supports_hiz_ccs_wt(devinfo, &res->surf, res->aux.usage))
-         break;
       return false;
+   case ISL_AUX_USAGE_HIZ_CCS_WT:
+      break;
    default:
       return false;
    }
@@ -953,8 +952,12 @@ iris_resource_texture_aux_usage(struct iris_context *ice,
       break;
 
    case ISL_AUX_USAGE_HIZ_CCS:
+      assert(!iris_sample_with_depth_aux(devinfo, res));
+      return ISL_AUX_USAGE_NONE;
+
+   case ISL_AUX_USAGE_HIZ_CCS_WT:
       if (iris_sample_with_depth_aux(devinfo, res))
-         return ISL_AUX_USAGE_CCS_E;
+         return ISL_AUX_USAGE_HIZ_CCS_WT;
       break;
 
    case ISL_AUX_USAGE_MCS:

diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index 7ca6097840af2c6cacecf82f34e6a6437346fd98..8142c42f3dcea035049033abce4a5604a8c798ba 100644 (file)
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -480,8 +480,18 @@ iris_resource_configure_aux(struct iris_screen *screen,
       res->aux.possible_usages |=
          1 << (has_ccs ? ISL_AUX_USAGE_MCS_CCS : ISL_AUX_USAGE_MCS);
    } else if (has_hiz) {
-      res->aux.possible_usages |=
-         1 << (has_ccs ? ISL_AUX_USAGE_HIZ_CCS : ISL_AUX_USAGE_HIZ);
+      if (!has_ccs) {
+         res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
+      } else if (res->surf.samples == 1 &&
+                 (res->surf.usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
+         /* If this resource is single-sampled and will be used as a texture,
+          * put the HiZ surface in write-through mode so that we can sample
+          * from it.
+          */
+         res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS_WT;
+      } else {
+         res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS;
+      }
    } else if (has_ccs) {
       if (want_ccs_e_for_format(devinfo, res->surf.format))
          res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E;
@@ -500,11 +510,8 @@ iris_resource_configure_aux(struct iris_screen *screen,
    if (!devinfo->has_sample_with_hiz || res->surf.samples > 1)
       res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);
 
-   /* We don't always support sampling with HIZ_CCS. But when we do, treat it
-    * as CCS_E.*/
+   /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
    res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ_CCS);
-   if (isl_surf_supports_hiz_ccs_wt(devinfo, &res->surf, res->aux.usage))
-      res->aux.sampler_usages |= 1 << ISL_AUX_USAGE_CCS_E;
 
    enum isl_aux_state initial_state;
    *aux_size_B = 0;
@@ -517,6 +524,7 @@ iris_resource_configure_aux(struct iris_screen *screen,
       return !res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE;
    case ISL_AUX_USAGE_HIZ:
    case ISL_AUX_USAGE_HIZ_CCS:
+   case ISL_AUX_USAGE_HIZ_CCS_WT:
       initial_state = ISL_AUX_STATE_AUX_INVALID;
       break;
    case ISL_AUX_USAGE_MCS:

diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index b8a68ffdbecce03acee2d0ecae2659773e3aa7d9..27299d568693aea7f66d420a8c673aae32dbf24e 100644 (file)
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -805,7 +805,7 @@ blorp_can_hiz_clear_depth(const struct gen_device_info *devinfo,
       if (x0 % align_px_w || y0 % align_px_h ||
           x1 % align_px_w || y1 % align_px_h)
          return false;
-   } else if (isl_surf_supports_hiz_ccs_wt(devinfo, surf, aux_usage)) {
+   } else if (aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
       /* We have to set the WM_HZ_OP::FullSurfaceDepthandStencilClear bit
        * whenever we clear an uninitialized HIZ buffer (as some drivers
        * currently do). However, this bit seems liable to clear 16x8 pixels in