fhdl/verilog: avoid reg initialization in printheader when reset is not an int.

We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index c1cfc690e8b178b11301353ee67c43472b7b86ac..eac214c6077318eaeedc3f05c8f1588c84b54b0c 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -172,7 +172,11 @@ def _printheader(f, ios, name, ns):
                if sig in wires:
                        r += "wire " + _printsig(ns, sig) + ";\n"
                else:
-                       r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
+                       if isinstance(sig.reset, int):
+                               resetexpr = " = " + _printexpr(ns, sig.reset)[0]
+                       else:
+                               resetexpr = ""
+                       r += "reg " + _printsig(ns, sig) + resetexpr + ";\n"
        r += "\n"
        return r