radeonsi: emit VS_STATE register explicitly from si_draw_vbo
authorNicolai Hähnle <nicolai.haehnle@amd.com>
Wed, 12 Apr 2017 08:00:18 +0000 (10:00 +0200)
committerNicolai Hähnle <nicolai.haehnle@amd.com>
Thu, 13 Apr 2017 15:30:18 +0000 (17:30 +0200)
We will merge other derived state information into this register.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeonsi/si_hw_context.c
src/gallium/drivers/radeonsi/si_pipe.h
src/gallium/drivers/radeonsi/si_shader.h
src/gallium/drivers/radeonsi/si_state.c
src/gallium/drivers/radeonsi/si_state.h
src/gallium/drivers/radeonsi/si_state_draw.c

index c80b884970a65f28d8c6ca9b76d42a4dd100daab..e51abfc5c53989a81e1fb96bf6250477d42b023b 100644 (file)
@@ -257,6 +257,7 @@ void si_begin_new_cs(struct si_context *ctx)
        ctx->last_multi_vgt_param = -1;
        ctx->last_rast_prim = -1;
        ctx->last_sc_line_stipple = ~0;
+       ctx->last_vs_state = ~0;
        ctx->last_ls = NULL;
        ctx->last_tcs = NULL;
        ctx->last_tes_sh_base = -1;
index daf29325f76e1514fc71172858e14f3f03ac024c..09788316a4935f1a431efec052f5e1dc74bbbffb 100644 (file)
@@ -348,6 +348,8 @@ struct si_context {
        int                     last_multi_vgt_param;
        int                     last_rast_prim;
        unsigned                last_sc_line_stipple;
+       unsigned                current_vs_state;
+       unsigned                last_vs_state;
        enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
        bool                    gs_tri_strip_adj_fix;
 
index 17ffc5d8c78b9dc993411b50db8dc1d3b0ce4a8e..4a0f27045640ff44d4bee62c6b8b22727616bfa5 100644 (file)
@@ -226,6 +226,11 @@ enum {
        SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
 };
 
+/* Fields of driver-defined VS state SGPR. */
+/* Clamp vertex color output (only used in VS as VS). */
+#define S_VS_STATE_CLAMP_VERTEX_COLOR(x)       (((unsigned)(x) & 0x1) << 0)
+#define C_VS_STATE_CLAMP_VERTEX_COLOR          0xFFFFFFFE
+
 /* SI-specific system values. */
 enum {
        TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT,
index 4a6b61587fb77cbf68c1b1bdf82cadf1412fbf49..a55f024c843718f528e4ec64885fc3f474a1b4ee 100644 (file)
@@ -796,6 +796,7 @@ static void *si_create_rs_state(struct pipe_context *ctx,
        rs->uses_poly_offset = state->offset_point || state->offset_line ||
                               state->offset_tri;
        rs->clamp_fragment_color = state->clamp_fragment_color;
+       rs->clamp_vertex_color = state->clamp_vertex_color;
        rs->flatshade = state->flatshade;
        rs->sprite_coord_enable = state->sprite_coord_enable;
        rs->rasterizer_discard = state->rasterizer_discard;
@@ -862,8 +863,6 @@ static void *si_create_rs_state(struct pipe_context *ctx,
                                   state->fill_back != PIPE_POLYGON_MODE_FILL) |
                S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
                S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
-       si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
-                      SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
 
        /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
        for (i = 0; i < 3; i++) {
@@ -926,6 +925,9 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
                        si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
        }
 
+       sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
+       sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
+
        r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
 
        si_pm4_bind_state(sctx, rasterizer, rs);
index aad1c8343f1c1af158fb0c01ab97f2432d402523..6257299fc3aa3e1028e79be71e28bf65ab88e66d 100644 (file)
@@ -74,6 +74,7 @@ struct si_state_rasterizer {
        bool                    poly_smooth;
        bool                    uses_poly_offset;
        bool                    clamp_fragment_color;
+       bool                    clamp_vertex_color;
        bool                    rasterizer_discard;
        bool                    scissor_enable;
        bool                    clip_halfz;
index 65b33cee4efd9d727b2a93c44e804b771c27c7fc..54e02d217a98f4d6dc6d6e78591a0a747dc02238 100644 (file)
@@ -494,6 +494,19 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
        sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
 }
 
+static void si_emit_vs_state(struct si_context *sctx)
+{
+       if (sctx->current_vs_state != sctx->last_vs_state) {
+               struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+
+               radeon_set_sh_reg(cs,
+                       R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_VS_STATE_BITS * 4,
+                       sctx->current_vs_state);
+
+               sctx->last_vs_state = sctx->current_vs_state;
+       }
+}
+
 static void si_emit_draw_registers(struct si_context *sctx,
                                   const struct pipe_draw_info *info,
                                   unsigned num_patches)
@@ -1291,6 +1304,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
        si_emit_rasterizer_prim_state(sctx);
        if (sctx->tes_shader.cso)
                si_emit_derived_tess_state(sctx, info, &num_patches);
+       si_emit_vs_state(sctx);
        si_emit_draw_registers(sctx, info, num_patches);
 
        si_ce_pre_draw_synchronization(sctx);