radv: simplify checking for Navi1x chips

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4702>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 6e5809ac492aba5a48cdb53622d23ce292fdaec8..a2526186e76bd907e17aa4a4684f1766cb5b013c 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3870,9 +3870,7 @@ void radv_CmdBindPipeline(
                /* Prefetch all pipeline shaders at first draw time. */
                cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
 
-               if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 ||
-                    cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 ||
-                    cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) &&
+               if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 &&
                    cmd_buffer->state.emitted_pipeline &&
                    radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) &&
                    !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) {

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 29a891627f7099ac0e26f0b01b472e2c2c9a9c0b..e707ba8c907174b5aec0a48ca5a6c19f4131ea17 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1892,12 +1892,10 @@ radv_llvm_export_vs(struct radv_shader_context *ctx,
                        outinfo->pos_exports++;
        }
 
-       /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
+       /* GFX10 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
         * Setting valid_mask=1 prevents it and has no other effect.
         */
-       if (ctx->ac.family == CHIP_NAVI10 ||
-           ctx->ac.family == CHIP_NAVI12 ||
-           ctx->ac.family == CHIP_NAVI14)
+       if (ctx->ac.chip_class == GFX10)
                pos_args[0].valid_mask = 1;
 
        pos_idx = 0;

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 448cbebf2adc3e2d0e5e7cfd01c6dc19b6c6cefb..984a095aad8a742318b9aacd7591fd7906440dc9 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4082,9 +4082,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
         *
         * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
         */
-       if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
-            pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
-            pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
+       if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
            !radv_pipeline_has_tess(pipeline) &&
            ngg_state->hw_max_esverts != 256) {
                ge_cntl &= C_03096C_VERT_GRP_SIZE;

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 43d288145d75b4f91a84008c3adde47fb56b4b87..a9083f33f7ba1dedf80ce8b88cb97b5ccbe6a267 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -416,9 +416,7 @@ si_emit_graphics(struct radv_physical_device *physical_device,
                                  S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
                radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
 
-               if (physical_device->rad_info.family == CHIP_NAVI10 ||
-                   physical_device->rad_info.family == CHIP_NAVI12 ||
-                   physical_device->rad_info.family == CHIP_NAVI14) {
+               if (physical_device->rad_info.chip_class == GFX10) {
                        /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
                        radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
                        radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));