genxml/hsw: Add L3 cache control registers

These were added to the i965 driver in
5912da45a69923afa1b7f2eb5bb371d848813c41.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 698d93f12aef255564710661a1ad3108d2326ba6..2258dee3960440206181b90223e19b2a3f98c38a 100644 (file)
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2932,4 +2932,12 @@
     <field name="T Low Bandwidth" start="21" end="21" type="uint"/>
   </register>
 
+  <register name="SCRATCH1" length="1" num="0xb038">
+    <field name="L3 Atomic Disable" start="27" end="27" type="uint"/>
+  </register>
+
+  <register name="CHICKEN3" length="1" num="0xe49c">
+    <field name="L3 Atomic Disable" start="6" end="6" type="uint"/>
+  </register>
+
 </genxml>