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diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 5d5a859de827c78954977fb8ca249338966ad263..90000f07007253d1ad9b6b80d5301e53db5bfbfb 100644 (file)
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -93,8 +93,8 @@ class SVP64RMModeDecode(Elaboratable):
 
         self.saturate = Signal(SVP64sat)
         self.RC1 = Signal()
-        self.cr_sel = Signal(2)
-        self.inv = Signal(1)
+        self.cr_sel = Signal(2)  # bit of CR to test (index 0-3)
+        self.inv = Signal(1)     # and whether it's inverted (like branch BO)
         self.map_evm = Signal(1)
         self.map_crm = Signal(1)
         self.ldstmode = Signal(SVP64LDSTmode) # LD/ST Mode (strided type)