boards/targets: make sys_clk_freq a parameter

Most of the targets can now generate an abritrary sys_clk_freq from onboard XO.

diff --git a/litex/boards/targets/ac701.py b/litex/boards/targets/ac701.py
index a0b4ba5a742e5e989bdf007109fc64426f12be5b..0933866ebed0b70a2fc5cd048f3537257d109ba0 100755 (executable)
--- a/litex/boards/targets/ac701.py
+++ b/litex/boards/targets/ac701.py
@@ -51,9 +51,8 @@ class BaseSoC(SoCSDRAM):
         "ddrphy":    16,
     }
     csr_map.update(SoCSDRAM.csr_map)
-    def __init__(self, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = ac701.Platform()
-        sys_clk_freq = int(100e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                          integrated_rom_size=0x8000,
                          integrated_sram_size=0x8000,

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index ba058c5f5209fbc53212eaf59f402c6bacd6d3b0..98cc0adc6380b80c28813bcdcc727fef64ca34bf 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -55,9 +55,8 @@ class BaseSoC(SoCSDRAM):
         "ddrphy":    16,
     }
     csr_map.update(SoCSDRAM.csr_map)
-    def __init__(self, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = arty.Platform()
-        sys_clk_freq = int(100e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                          integrated_rom_size=0x8000,
                          integrated_sram_size=0x8000,

diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index c51c1a1164b3623d85bcae521d3acbb481979ea9..81a3e4a2f4f19df83e67636a9a4870c63a3118c5 100755 (executable)
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -96,9 +96,9 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+        assert sys_clk_freq == int(100e6)
         platform = de0nano.Platform()
-        sys_clk_freq = int(100e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                           integrated_rom_size=0x8000,
                           **kwargs)

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index efd739795d52af2402030e8635db1ee303bcaa6b..1b9e1d6cf42ec20501eeaf8098f1bdf1b874e02f 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -46,9 +46,8 @@ class BaseSoC(SoCSDRAM):
         "ddrphy":    16,
     }
     csr_map.update(SoCSDRAM.csr_map)
-    def __init__(self, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
         platform = genesys2.Platform()
-        sys_clk_freq = int(125e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                          integrated_rom_size=0x8000,
                          integrated_sram_size=0x8000,

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 14b53239c3034ff62a9ef0d51bf5ff1f79b34373..954fe954bfba1d5acc2465cd6b8c802de597b3dc 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -46,9 +46,8 @@ class BaseSoC(SoCSDRAM):
         "ddrphy":    16,
     }
     csr_map.update(SoCSDRAM.csr_map)
-    def __init__(self, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
         platform = kc705.Platform()
-        sys_clk_freq = int(125e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                          integrated_rom_size=0x8000,
                          integrated_sram_size=0x8000,

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index 06eda9e2e7500260cce0f2dafc1c7c6e066aac0b..9067ceedf3579cc2bf4561abe7838b91b0e6b0e5 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -82,9 +82,8 @@ class BaseSoC(SoCSDRAM):
         "ddrphy":    16,
     }
     csr_map.update(SoCSDRAM.csr_map)
-    def __init__(self, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
         platform = kcu105.Platform()
-        sys_clk_freq = int(125e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                          integrated_rom_size=0x8000,
                          integrated_sram_size=0x8000,

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 20e2113e4f14ae3e4a9173ccbc8c1b342b266205..dbd392513b3cacb57dd13c3c311c0b906f90de42 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -81,9 +81,9 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, **kwargs):
+    def __init__(self, sys_clk_freq=int(80e6), **kwargs):
+        assert sys_clk_freq == int(80e6)
         platform = minispartan6.Platform()
-        sys_clk_freq = int(80e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                           integrated_rom_size=0x8000,
                           **kwargs)

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index 5adf51d8d2d9f83840057cf41726582869c53a5d..56df51827292a71a0fe248de6488115ee851422a 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -47,9 +47,8 @@ class BaseSoC(SoCSDRAM):
         "ddrphy": 16,
     }
     csr_map.update(SoCSDRAM.csr_map)
-    def __init__(self, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = nexys4ddr.Platform()
-        sys_clk_freq = int(100e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                          integrated_rom_size=0x8000,
                          integrated_sram_size=0x8000,

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index d949f57af121fb281e525858f3774a3737f3ccbd..7125d1a61e25a7f893a58a8e1699023bbfa70b6e 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -50,9 +50,8 @@ class BaseSoC(SoCSDRAM):
         "ddrphy": 16,
     }
     csr_map.update(SoCSDRAM.csr_map)
-    def __init__(self, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
         platform = nexys_video.Platform()
-        sys_clk_freq = int(100e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                          integrated_rom_size=0x8000,
                          integrated_sram_size=0x8000,

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 9e807d62eb41ed65ab4067b2215ed6a621002857..2c88a661818ca94cc8e866ac1d1e7bcf003f1213 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -17,7 +17,7 @@ from litedram.phy import GENSDRPHY
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
-    def __init__(self, platform):
+    def __init__(self, platform, sys_clk_freq):
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
 
@@ -35,8 +35,8 @@ class _CRG(Module):
         self.submodules.pll = pll = ECP5PLL()
         self.comb += pll.reset.eq(rst)
         pll.register_clkin(clk25, 25e6)
-        pll.create_clkout(self.cd_sys, 50e6, phase=11)
-        pll.create_clkout(self.cd_sys_ps, 50e6, phase=20)
+        pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
+        pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
         self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
 
         # sdram clock
@@ -56,7 +56,7 @@ class BaseSoC(SoCSDRAM):
                           integrated_rom_size=0x8000,
                           **kwargs)
 
-        self.submodules.crg = _CRG(platform)
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
 
         if not self.integrated_main_ram_size:
             self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index e28ccb3e67064968002e4a0e3b48fcf4297ef8ac..bb92c1327f158ed1d192792b77f69c488716f373 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -77,9 +77,8 @@ class BaseSoC(SoCSDRAM):
         "ddrphy":    16,
     }
     csr_map.update(SoCSDRAM.csr_map)
-    def __init__(self, toolchain="diamond", **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
         platform = versa_ecp5.Platform(toolchain=toolchain)
-        sys_clk_freq = int(75e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                           integrated_rom_size=0x8000,
                           **kwargs)