dev, arm: accept and ignore writes to GIC APRn registers

Otherwise the Linux kernel v4.17 boot fails with error:

Tried to write Gic cpu at offset 0xd0

Change-Id: Ie8063212c9e2b29e2e4766801b4b9538e9eccbf8
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11590
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index f918f7783fed1a119f2d8db8020d678a04964874..b0c4e99eec8fded857124fe23ea0fcd463bea432 100644 (file)
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2013, 2015-2017 ARM Limited
+ * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -602,6 +602,12 @@ Pl390::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
                 ctx, iar.ack_id, iar.cpu_id);
         break;
       }
+      case GICC_APR0:
+      case GICC_APR1:
+      case GICC_APR2:
+      case GICC_APR3:
+        warn("GIC APRn write ignored because not implemented: %#x\n", daddr);
+        break;
       default:
         panic("Tried to write Gic cpu at offset %#x\n", daddr);
         break;

diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index dc45d25d7cdadca521c5a9df6f66fd5c494a6ff4..b4e880bf2eda3bbad3b82c5199fa0b523bdf898b 100644 (file)
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2013, 2015-2017 ARM Limited
+ * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -105,6 +105,10 @@ class Pl390 : public BaseGic, public BaseGicRegisters
         GICC_RPR   = 0x14, // running priority
         GICC_HPPIR = 0x18, // highest pending interrupt
         GICC_ABPR  = 0x1c, // aliased binary point
+        GICC_APR0  = 0xd0, // active priority register 0
+        GICC_APR1  = 0xd4, // active priority register 1
+        GICC_APR2  = 0xd8, // active priority register 2
+        GICC_APR3  = 0xdc, // active priority register 3
         GICC_IIDR  = 0xfc, // cpu interface id register
 
         CPU_SIZE   = 0xff