HexFile::~HexFile()
{
+ if (fp != NULL)
+ fclose(fp);
}
bool
std::memset(stageActive, 0, numStages);
}
+ActivityRecorder::~ActivityRecorder()
+{
+ delete[] stageActive;
+}
+
void
ActivityRecorder::activity()
{
public:
ActivityRecorder(const std::string &name, int num_stages,
int longest_latency, int count);
+ ~ActivityRecorder();
/** Records that there is activity this cycle. */
void activity();
BaseCPU::~BaseCPU()
{
+ delete profileEvent;
+ delete[] comLoadEventQueue;
+ delete[] comInstEventQueue;
}
void
PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
unsigned _numPhysicalFloatRegs);
+ /**
+ * Destructor to free resources
+ */
+ ~PhysRegFile();
+
//Everything below should be pretty well identical to the normal
//register file that exists within AlphaISA class.
//The duplication is unfortunate but it's better than having
memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
}
+template <class Impl>
+PhysRegFile<Impl>::~PhysRegFile()
+{
+ delete intRegFile;
+ delete floatRegFile;
+}
+
#endif
vncserver->setFramebufferAddr(dmaBuffer);
}
+Pl111::~Pl111()
+{
+ delete[] dmaBuffer;
+}
+
// read registers and frame buffer
Tick
Pl111::read(PacketPtr pkt)
return dynamic_cast<const Params *>(_params);
}
Pl111(const Params *p);
+ ~Pl111();
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
if (buffer)
delete [] buffer;
+ delete interface;
delete listener;
}
txFifo.clear();
}
+IGbE::~IGbE()
+{
+ delete etherInt;
+}
+
void
IGbE::init()
{
IGbE::DescCache<T>::~DescCache()
{
reset();
+ delete[] fetchBuf;
+ delete[] wbBuf;
}
template<class T>
}
IGbE(const Params *params);
- ~IGbE() {}
+ ~IGbE();
virtual void init();
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
}
NSGigE::~NSGigE()
-{}
+{
+ delete interface;
+}
/**
* This is to write to the PCI general configuration registers
MSHR::~MSHR()
{
+ delete[] targets;
+ delete[] deferredTargets;
}
//assert(check());
}
+FALRU::~FALRU()
+{
+ if (numCaches)
+ delete[] cacheBoundaries;
+
+ delete[] blks;
+}
+
void
FALRU::regStats(const string &name)
{
* @param hit_latency The hit latency of the cache.
*/
FALRU(unsigned blkSize, unsigned size, unsigned hit_latency);
+ ~FALRU();
/**
* Register the stats for this object.
delete [] dataStore;
delete [] tagStore;
delete [] sets;
+ delete [] dataBlks;
}
/* register cache stats */
entry = new TheISA::TlbEntry();
entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
pTable[vaddr] = *entry;
+ delete entry;
++i;
}
}
}
}
+Checkpoint::~Checkpoint()
+{
+ delete db;
+}
bool
Checkpoint::find(const string §ion, const string &entry, string &value)
public:
Checkpoint(const std::string &cpt_dir);
+ ~Checkpoint();
const std::string cptDir;