Bump the IRQ for liteeth based targets.
authorTim 'mithro' Ansell <mithro@mithis.com>
Sun, 29 Oct 2017 17:39:01 +0000 (10:39 -0700)
committerTim 'mithro' Ansell <mithro@mithis.com>
Mon, 30 Oct 2017 02:45:52 +0000 (19:45 -0700)
litex/boards/targets/arty.py
litex/boards/targets/kc705.py
litex/boards/targets/nexys_video.py
litex/boards/targets/sim.py
litex/boards/targets/simple.py

index 75d58a9b5965f9e921a870c287b197423a00ffd1..64d892f87b323833b662f7fff39f4527358ba945 100755 (executable)
@@ -124,7 +124,7 @@ class MiniSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 
index 37297f330c2129fe95f1e791517e4ad3ddca1fd2..541d3dea96445a060c1ba87bfd6e46620ec43c1f 100755 (executable)
@@ -104,7 +104,7 @@ class MiniSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 
index 75774e9458bb4a5dbd0524c77d663ddc0fe87f14..77b54688b88b0fb9606b3ae410e46a69254596a7 100755 (executable)
@@ -113,7 +113,7 @@ class MiniSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 
index 1624441fc86a1f2d9ab2060e72333a1e03449239..04371fd9f70dc944b2bbf65922b0455c8d7416fb 100755 (executable)
@@ -68,7 +68,7 @@ class MiniSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 
index 179581b4379d438d6e231eeb1aa0a8788fcd0585..88c8afd37ab4f73fb7fe1df91561aa6f9a691506 100755 (executable)
@@ -30,7 +30,7 @@ class MiniSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)