* m10300-opc.c: Reorder "movbu" and "movhu" instructions too.

Why oh why didn't they take our advice about register prefixing.  It would
have avoided the ambigious syntax issues.  Sigh.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fe82b5af85b6ee620500225df2008cbdd1ce609f..e75da412c812c86174e4ff6c8f8d2b49a1ac5f03 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,4 +1,8 @@
 start-sanitize-am33
+Tue Jun 30 09:59:37 1998  Jeffrey A Law  (law@cygnus.com)
+
+       * m10300-opc.c: Reorder "movbu" and "movhu" instructions too.
+
 Mon Jun 29 14:54:32 1998  Jeffrey A Law  (law@cygnus.com)
 
        * m10300-opc.c: Reorder more instructions so that we do not

diff --git a/opcodes/m10300-opc.c b/opcodes/m10300-opc.c
index 3989c90461bb4f329d015e6619a195172535b580..b0498cdea2057d6420613b997b786f30260f8cd1 100644 (file)
--- a/opcodes/m10300-opc.c
+++ b/opcodes/m10300-opc.c
@@ -555,25 +555,19 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "movbu",     0xf040,      0xfff0,     FMT_D0, 0,     {MEM(AM0), DN1}},
 { "movbu",     0xf84000,    0xfff000,   FMT_D1, 0,     {MEM2(SD8, AM0), DN1}},
 { "movbu",     0xfa400000,  0xfff00000, FMT_D2, 0,     {MEM2(SD16, AM0), DN1}},
-{ "movbu",     0xfc400000,  0xfff00000, FMT_D4, 0,     {MEM2(IMM32,AM0), DN1}},
 { "movbu",     0xf8b800,    0xfffcff,   FMT_D1, 0,     {MEM(SP), DN0}},
 { "movbu",     0xf8b800,    0xfffc00,   FMT_D1, 0,     {MEM2(IMM8, SP), DN0}},
 { "movbu",     0xfab80000,  0xfffc0000, FMT_D2, 0,     {MEM2(IMM16, SP), DN0}},
-{ "movbu",     0xfcb80000,  0xfffc0000, FMT_D4, 0,     {MEM2(IMM32, SP), DN0}},
 { "movbu",     0xf400,      0xffc0,     FMT_D0, 0,     {MEM2(DI, AM0), DN2}},
 { "movbu",     0x340000,    0xfc0000,   FMT_S2, 0,     {MEM(IMM16_MEM), DN0}},
-{ "movbu",     0xfca80000,  0xfffc0000, FMT_D4, 0,     {MEM(IMM32_MEM), DN0}},
 { "movbu",     0xf050,      0xfff0,     FMT_D0, 0,     {DM1, MEM(AN0)}},
 { "movbu",     0xf85000,    0xfff000,   FMT_D1, 0,     {DM1, MEM2(SD8, AN0)}},
 { "movbu",     0xfa500000,  0xfff00000, FMT_D2, 0,     {DM1, MEM2(SD16, AN0)}},
-{ "movbu",     0xfc500000,  0xfff00000, FMT_D4, 0,     {DM1, MEM2(IMM32,AN0)}},
 { "movbu",     0xf89200,    0xfff3ff,   FMT_D1, 0,     {DM1, MEM(SP)}},
 { "movbu",     0xf89200,    0xfff300,   FMT_D1, 0,     {DM1, MEM2(IMM8, SP)}},
 { "movbu",     0xfa920000,  0xfff30000, FMT_D2, 0,     {DM1, MEM2(IMM16, SP)}},
-{ "movbu",     0xfc920000,  0xfff30000, FMT_D4, 0,     {DM1, MEM2(IMM32, SP)}},
 { "movbu",     0xf440,      0xffc0,     FMT_D0, 0,     {DM2, MEM2(DI, AN0)}},
 { "movbu",     0x020000,    0xf30000,   FMT_S2, 0,     {DM1, MEM(IMM16_MEM)}},
-{ "movbu",     0xfc820000,  0xfff30000, FMT_D4, 0,     {DM1, MEM(IMM32_MEM)}},
 /* start-sanitize-am33 */
 { "movbu",     0xf92a00,    0xffff00,   FMT_D6, AM33,  {MEM(RM0), RN2}},
 { "movbu",     0xf93a00,    0xffff00,   FMT_D6, AM33,  {RM2, MEM(RN0)}},
@@ -581,54 +575,56 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "movbu",     0xf9ba00,    0xffff0f,   FMT_D6, AM33,  {RM2, MEM(SP)}},
 { "movbu",     0xfb2a0000,  0xffff0000, FMT_D7, AM33,  {MEM2(SD8, RM0), RN2}},
 { "movbu",     0xfd2a0000,  0xffff0000, FMT_D8, AM33,  {MEM2(SD24, RM0), RN2}},
-{ "movbu",     0xfe2a0000,  0xffff0000, FMT_D9, AM33,  {MEM2(IMM32_HIGH8,RM0),
-                                                        RN2}},
 { "movbu",     0xfb3a0000,  0xffff0000, FMT_D7, AM33,  {RM2, MEM2(SD8, RN0)}},
 { "movbu",     0xfd3a0000,  0xffff0000, FMT_D8, AM33,  {RM2, MEM2(SD24, RN0)}},
-{ "movbu",     0xfe3a0000,  0xffff0000, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
-                                                                  RN0)}},
 { "movbu",     0xfbaa0000,  0xffff0f00, FMT_D7, AM33,  {MEM2(SD8, SP), RN2}},
 { "movbu",     0xfdaa0000,  0xffff0f00, FMT_D8, AM33,  {MEM2(SD24, SP), RN2}},
-{ "movbu",     0xfeaa0000,  0xffff0f00, FMT_D9, AM33,  {MEM2(IMM32_HIGH8,SP),
-                                                        RN2}},
 { "movbu",     0xfbba0000,  0xffff0f00, FMT_D7, AM33,  {RM2, MEM2(SD8, SP)}},
 { "movbu",     0xfdba0000,  0xffff0f00, FMT_D8, AM33,  {RM2, MEM2(SD24, SP)}},
-{ "movbu",     0xfeba0000,  0xffff0f00, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
-                                                                  SP)}},
 { "movbu",     0xfb2e0000,  0xffff0f00, FMT_D7, AM33,  {MEM(IMM8_MEM), RN2}},
 { "movbu",     0xfd2e0000,  0xffff0f00, FMT_D8, AM33,  {MEM(IMM24_MEM), RN2}},
-{ "movbu",     0xfe2e0000,  0xffff0f00, FMT_D9, AM33,  {MEM(IMM32_HIGH8_MEM),
-                                                        RN2}},
 { "movbu",     0xfb3e0000,  0xffff0f00, FMT_D7, AM33,  {RM2, MEM(IMM8_MEM)}},
 { "movbu",     0xfd3e0000,  0xffff0f00, FMT_D8, AM33,  {RM2, MEM(IMM24_MEM)}},
-{ "movbu",     0xfe3e0000,  0xffff0f00, FMT_D9, AM33,  {RM2,
-                                                        MEM(IMM32_HIGH8_MEM)}},
 { "movbu",     0xfbae0000,  0xffff000f, FMT_D7, AM33,  {MEM2(RI, RM0), RD2}},
 { "movbu",     0xfbbe0000,  0xffff000f, FMT_D7, AM33,  {RD2, MEM2(RI, RN0)}},
 /* end-sanitize-am33 */
+{ "movbu",     0xfc400000,  0xfff00000, FMT_D4, 0,     {MEM2(IMM32,AM0), DN1}},
+{ "movbu",     0xfcb80000,  0xfffc0000, FMT_D4, 0,     {MEM2(IMM32, SP), DN0}},
+{ "movbu",     0xfca80000,  0xfffc0000, FMT_D4, 0,     {MEM(IMM32_MEM), DN0}},
+{ "movbu",     0xfc500000,  0xfff00000, FMT_D4, 0,     {DM1, MEM2(IMM32,AN0)}},
+{ "movbu",     0xfc920000,  0xfff30000, FMT_D4, 0,     {DM1, MEM2(IMM32, SP)}},
+{ "movbu",     0xfc820000,  0xfff30000, FMT_D4, 0,     {DM1, MEM(IMM32_MEM)}},
+/* start-sanitize-am33 */
+{ "movbu",     0xfe2a0000,  0xffff0000, FMT_D9, AM33,  {MEM2(IMM32_HIGH8,RM0),
+                                                        RN2}},
+{ "movbu",     0xfe3a0000,  0xffff0000, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
+                                                                  RN0)}},
+{ "movbu",     0xfeaa0000,  0xffff0f00, FMT_D9, AM33,  {MEM2(IMM32_HIGH8,SP),
+                                                        RN2}},
+{ "movbu",     0xfeba0000,  0xffff0f00, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
+                                                                  SP)}},
+{ "movbu",     0xfe2e0000,  0xffff0f00, FMT_D9, AM33,  {MEM(IMM32_HIGH8_MEM),
+                                                        RN2}},
+{ "movbu",     0xfe3e0000,  0xffff0f00, FMT_D9, AM33,  {RM2,
+                                                        MEM(IMM32_HIGH8_MEM)}},
+/* end-sanitize-am33 */
 
 { "movhu",     0xf060,      0xfff0,     FMT_D0, 0,     {MEM(AM0), DN1}},
 { "movhu",     0xf86000,    0xfff000,   FMT_D1, 0,     {MEM2(SD8, AM0), DN1}},
 { "movhu",     0xfa600000,  0xfff00000, FMT_D2, 0,     {MEM2(SD16, AM0), DN1}},
-{ "movhu",     0xfc600000,  0xfff00000, FMT_D4, 0,     {MEM2(IMM32,AM0), DN1}},
 { "movhu",     0xf8bc00,    0xfffcff,   FMT_D1, 0,     {MEM(SP), DN0}},
 { "movhu",     0xf8bc00,    0xfffc00,   FMT_D1, 0,     {MEM2(IMM8, SP), DN0}},
 { "movhu",     0xfabc0000,  0xfffc0000, FMT_D2, 0,     {MEM2(IMM16, SP), DN0}},
-{ "movhu",     0xfcbc0000,  0xfffc0000, FMT_D4, 0,     {MEM2(IMM32, SP), DN0}},
 { "movhu",     0xf480,      0xffc0,     FMT_D0, 0,     {MEM2(DI, AM0), DN2}},
 { "movhu",     0x380000,    0xfc0000,   FMT_S2, 0,     {MEM(IMM16_MEM), DN0}},
-{ "movhu",     0xfcac0000,  0xfffc0000, FMT_D4, 0,     {MEM(IMM32_MEM), DN0}},
 { "movhu",     0xf070,      0xfff0,     FMT_D0, 0,     {DM1, MEM(AN0)}},
 { "movhu",     0xf87000,    0xfff000,   FMT_D1, 0,     {DM1, MEM2(SD8, AN0)}},
 { "movhu",     0xfa700000,  0xfff00000, FMT_D2, 0,     {DM1, MEM2(SD16, AN0)}},
-{ "movhu",     0xfc700000,  0xfff00000, FMT_D4, 0,     {DM1, MEM2(IMM32,AN0)}},
 { "movhu",     0xf89300,    0xfff3ff,   FMT_D1, 0,     {DM1, MEM(SP)}},
 { "movhu",     0xf89300,    0xfff300,   FMT_D1, 0,     {DM1, MEM2(IMM8, SP)}},
 { "movhu",     0xfa930000,  0xfff30000, FMT_D2, 0,     {DM1, MEM2(IMM16, SP)}},
-{ "movhu",     0xfc930000,  0xfff30000, FMT_D4, 0,     {DM1, MEM2(IMM32, SP)}},
 { "movhu",     0xf4c0,      0xffc0,     FMT_D0, 0,     {DM2, MEM2(DI, AN0)}},
 { "movhu",     0x030000,    0xf30000,   FMT_S2, 0,     {DM1, MEM(IMM16_MEM)}},
-{ "movhu",     0xfc830000,  0xfff30000, FMT_D4, 0,     {DM1, MEM(IMM32_MEM)}},
 /* start-sanitize-am33 */
 { "movhu",     0xf94a00,    0xffff00,   FMT_D6, AM33,  {MEM(RM0), RN2}},
 { "movhu",     0xf95a00,    0xffff00,   FMT_D6, AM33,  {RM2, MEM(RN0)}},
@@ -638,30 +634,38 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "movhu",     0xf9fa00,    0xffff00,   FMT_D6, AM33,  {RM2, MEMINC(RN0)}},
 { "movhu",     0xfb4a0000,  0xffff0000, FMT_D7, AM33,  {MEM2(SD8, RM0), RN2}},
 { "movhu",     0xfd4a0000,  0xffff0000, FMT_D8, AM33,  {MEM2(SD24, RM0), RN2}},
-{ "movhu",     0xfe4a0000,  0xffff0000, FMT_D9, AM33,  {MEM2(IMM32_HIGH8,RM0),
-                                                        RN2}},
 { "movhu",     0xfb5a0000,  0xffff0000, FMT_D7, AM33,  {RM2, MEM2(SD8, RN0)}},
 { "movhu",     0xfd5a0000,  0xffff0000, FMT_D8, AM33,  {RM2, MEM2(SD24, RN0)}},
-{ "movhu",     0xfe5a0000,  0xffff0000, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
-                                                                  RN0)}},
 { "movhu",     0xfbca0000,  0xffff0f00, FMT_D7, AM33,  {MEM2(SD8, SP), RN2}},
 { "movhu",     0xfdca0000,  0xffff0f00, FMT_D8, AM33,  {MEM2(SD24, SP), RN2}},
-{ "movhu",     0xfeca0000,  0xffff0f00, FMT_D9, AM33,  {MEM2(IMM32_HIGH8, SP),
-                                                        RN2}},
 { "movhu",     0xfbda0000,  0xffff0f00, FMT_D7, AM33,  {RM2, MEM2(SD8, SP)}},
 { "movhu",     0xfdda0000,  0xffff0f00, FMT_D8, AM33,  {RM2, MEM2(SD24, SP)}},
-{ "movhu",     0xfeda0000,  0xffff0f00, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
-                                                                  SP)}},
 { "movhu",     0xfb4e0000,  0xffff0f00, FMT_D7, AM33,  {MEM(IMM8_MEM), RN2}},
 { "movhu",     0xfd4e0000,  0xffff0f00, FMT_D8, AM33,  {MEM(IMM24_MEM), RN2}},
+{ "movhu",     0xfbce0000,  0xffff000f, FMT_D7, AM33,  {MEM2(RI, RM0), RD2}},
+{ "movhu",     0xfbde0000,  0xffff000f, FMT_D7, AM33,  {RD2, MEM2(RI, RN0)}},
+/* end-sanitize-am33 */
+{ "movhu",     0xfc600000,  0xfff00000, FMT_D4, 0,     {MEM2(IMM32,AM0), DN1}},
+{ "movhu",     0xfcbc0000,  0xfffc0000, FMT_D4, 0,     {MEM2(IMM32, SP), DN0}},
+{ "movhu",     0xfcac0000,  0xfffc0000, FMT_D4, 0,     {MEM(IMM32_MEM), DN0}},
+{ "movhu",     0xfc700000,  0xfff00000, FMT_D4, 0,     {DM1, MEM2(IMM32,AN0)}},
+{ "movhu",     0xfc930000,  0xfff30000, FMT_D4, 0,     {DM1, MEM2(IMM32, SP)}},
+{ "movhu",     0xfc830000,  0xfff30000, FMT_D4, 0,     {DM1, MEM(IMM32_MEM)}},
+/* start-sanitize-am33 */
+{ "movhu",     0xfe4a0000,  0xffff0000, FMT_D9, AM33,  {MEM2(IMM32_HIGH8,RM0),
+                                                        RN2}},
+{ "movhu",     0xfe5a0000,  0xffff0000, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
+                                                                  RN0)}},
+{ "movhu",     0xfeca0000,  0xffff0f00, FMT_D9, AM33,  {MEM2(IMM32_HIGH8, SP),
+                                                        RN2}},
+{ "movhu",     0xfeda0000,  0xffff0f00, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
+                                                                  SP)}},
 { "movhu",     0xfe4e0000,  0xffff0f00, FMT_D9, AM33,  {MEM(IMM32_HIGH8_MEM),
                                                         RN2}},
 { "movhu",     0xfb5e0000,  0xffff0f00, FMT_D7, AM33,  {RM2, MEM(IMM8_MEM)}},
 { "movhu",     0xfd5e0000,  0xffff0f00, FMT_D8, AM33,  {RM2, MEM(IMM24_MEM)}},
 { "movhu",     0xfe5e0000,  0xffff0f00, FMT_D9, AM33,  {RM2,
                                                         MEM(IMM32_HIGH8_MEM)}},
-{ "movhu",     0xfbce0000,  0xffff000f, FMT_D7, AM33,  {MEM2(RI, RM0), RD2}},
-{ "movhu",     0xfbde0000,  0xffff000f, FMT_D7, AM33,  {RD2, MEM2(RI, RN0)}},
 /* end-sanitize-am33 */
 
 { "ext",       0xf2d0,      0xfffc,     FMT_D0, 0,     {DN0}},