Following MVE ACLE intrinsics have an issue with writeback to the base address.
vldrdq_gather_base_wb_s64, vldrdq_gather_base_wb_u64, vldrdq_gather_base_wb_z_s64, vldrdq_gather_base_wb_z_u64, vldrwq_gather_base_wb_s32, vldrwq_gather_base_wb_u32, vldrwq_gather_base_wb_z_s32, vldrwq_gather_base_wb_z_u32, vldrwq_gather_base_wb_f32, vldrwq_gather_base_wb_z_f32.
This patch fixes the bug reported in PR94317 by adding separate builtin calls to update the result and writeback to base address for the above intrinsics.
2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
PR target/94317
* config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
(LDRGBWBXU_Z_QUALIFIERS): Likewise.
* config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
intrinsic defintion by adding a new builtin call to writeback into base
address.
(__arm_vldrdq_gather_base_wb_u64): Likewise.
(__arm_vldrdq_gather_base_wb_z_s64): Likewise.
(__arm_vldrdq_gather_base_wb_z_u64): Likewise.
(__arm_vldrwq_gather_base_wb_s32): Likewise.
(__arm_vldrwq_gather_base_wb_u32): Likewise.
(__arm_vldrwq_gather_base_wb_z_s32): Likewise.
(__arm_vldrwq_gather_base_wb_z_u32): Likewise.
(__arm_vldrwq_gather_base_wb_f32): Likewise.
(__arm_vldrwq_gather_base_wb_z_f32): Likewise.
* config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
builtin's qualifier.
(vldrdq_gather_base_wb_z_u): Likewise.
(vldrwq_gather_base_wb_u): Likewise.
(vldrdq_gather_base_wb_u): Likewise.
(vldrwq_gather_base_wb_z_s): Likewise.
(vldrwq_gather_base_wb_z_f): Likewise.
(vldrdq_gather_base_wb_z_s): Likewise.
(vldrwq_gather_base_wb_s): Likewise.
(vldrwq_gather_base_wb_f): Likewise.
(vldrdq_gather_base_wb_s): Likewise.
(vldrwq_gather_base_nowb_z_u): Define builtin.
(vldrdq_gather_base_nowb_z_u): Likewise.
(vldrwq_gather_base_nowb_u): Likewise.
(vldrdq_gather_base_nowb_u): Likewise.
(vldrwq_gather_base_nowb_z_s): Likewise.
(vldrwq_gather_base_nowb_z_f): Likewise.
(vldrdq_gather_base_nowb_z_s): Likewise.
(vldrwq_gather_base_nowb_s): Likewise.
(vldrwq_gather_base_nowb_f): Likewise.
(vldrdq_gather_base_nowb_s): Likewise.
* config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
pattern.
(mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
(mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
(mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
(mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
(mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
(mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
(mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
(mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
(mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
(mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
(mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
gcc/testsuite/ChangeLog:
2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
PR target/94317
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Modify.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.
+2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ PR target/94317
+ * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
+ (LDRGBWBXU_Z_QUALIFIERS): Likewise.
+ * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
+ intrinsic defintion by adding a new builtin call to writeback into base
+ address.
+ (__arm_vldrdq_gather_base_wb_u64): Likewise.
+ (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
+ (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
+ (__arm_vldrwq_gather_base_wb_s32): Likewise.
+ (__arm_vldrwq_gather_base_wb_u32): Likewise.
+ (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
+ (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
+ (__arm_vldrwq_gather_base_wb_f32): Likewise.
+ (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
+ * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
+ builtin's qualifier.
+ (vldrdq_gather_base_wb_z_u): Likewise.
+ (vldrwq_gather_base_wb_u): Likewise.
+ (vldrdq_gather_base_wb_u): Likewise.
+ (vldrwq_gather_base_wb_z_s): Likewise.
+ (vldrwq_gather_base_wb_z_f): Likewise.
+ (vldrdq_gather_base_wb_z_s): Likewise.
+ (vldrwq_gather_base_wb_s): Likewise.
+ (vldrwq_gather_base_wb_f): Likewise.
+ (vldrdq_gather_base_wb_s): Likewise.
+ (vldrwq_gather_base_nowb_z_u): Define builtin.
+ (vldrdq_gather_base_nowb_z_u): Likewise.
+ (vldrwq_gather_base_nowb_u): Likewise.
+ (vldrdq_gather_base_nowb_u): Likewise.
+ (vldrwq_gather_base_nowb_z_s): Likewise.
+ (vldrwq_gather_base_nowb_z_f): Likewise.
+ (vldrdq_gather_base_nowb_z_s): Likewise.
+ (vldrwq_gather_base_nowb_s): Likewise.
+ (vldrwq_gather_base_nowb_f): Likewise.
+ (vldrdq_gather_base_nowb_s): Likewise.
+ * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
+ pattern.
+ (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
+ (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
+ (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
+ (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
+ (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
+ (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
+ (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
+ (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
+ (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
+ (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
+ (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
+
2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
#define QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS \
(arm_quinop_unone_unone_unone_unone_imm_unone_qualifiers)
+static enum arm_type_qualifiers
+arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate};
+#define LDRGBWBXU_QUALIFIERS (arm_ldrgbwbxu_qualifiers)
+
+static enum arm_type_qualifiers
+arm_ldrgbwbxu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate,
+ qualifier_unsigned};
+#define LDRGBWBXU_Z_QUALIFIERS (arm_ldrgbwbxu_z_qualifiers)
+
static enum arm_type_qualifiers
arm_ldrgbwbs_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_unsigned, qualifier_immediate};
__arm_vldrdq_gather_base_wb_s64 (uint64x2_t * __addr, const int __offset)
{
int64x2_t
- result = __builtin_mve_vldrdq_gather_base_wb_sv2di (*__addr, __offset);
- __addr += __offset;
+ result = __builtin_mve_vldrdq_gather_base_nowb_sv2di (*__addr, __offset);
+ *__addr = __builtin_mve_vldrdq_gather_base_wb_sv2di (*__addr, __offset);
return result;
}
__arm_vldrdq_gather_base_wb_u64 (uint64x2_t * __addr, const int __offset)
{
uint64x2_t
- result = __builtin_mve_vldrdq_gather_base_wb_uv2di (*__addr, __offset);
- __addr += __offset;
+ result = __builtin_mve_vldrdq_gather_base_nowb_uv2di (*__addr, __offset);
+ *__addr = __builtin_mve_vldrdq_gather_base_wb_uv2di (*__addr, __offset);
return result;
}
__arm_vldrdq_gather_base_wb_z_s64 (uint64x2_t * __addr, const int __offset, mve_pred16_t __p)
{
int64x2_t
- result = __builtin_mve_vldrdq_gather_base_wb_z_sv2di (*__addr, __offset, __p);
- __addr += __offset;
+ result = __builtin_mve_vldrdq_gather_base_nowb_z_sv2di (*__addr, __offset, __p);
+ *__addr = __builtin_mve_vldrdq_gather_base_wb_z_sv2di (*__addr, __offset, __p);
return result;
}
__arm_vldrdq_gather_base_wb_z_u64 (uint64x2_t * __addr, const int __offset, mve_pred16_t __p)
{
uint64x2_t
- result = __builtin_mve_vldrdq_gather_base_wb_z_uv2di (*__addr, __offset, __p);
- __addr += __offset;
+ result = __builtin_mve_vldrdq_gather_base_nowb_z_uv2di (*__addr, __offset, __p);
+ *__addr = __builtin_mve_vldrdq_gather_base_wb_z_uv2di (*__addr, __offset, __p);
return result;
}
__arm_vldrwq_gather_base_wb_s32 (uint32x4_t * __addr, const int __offset)
{
int32x4_t
- result = __builtin_mve_vldrwq_gather_base_wb_sv4si (*__addr, __offset);
- __addr += __offset;
+ result = __builtin_mve_vldrwq_gather_base_nowb_sv4si (*__addr, __offset);
+ *__addr = __builtin_mve_vldrwq_gather_base_wb_sv4si (*__addr, __offset);
return result;
}
__arm_vldrwq_gather_base_wb_u32 (uint32x4_t * __addr, const int __offset)
{
uint32x4_t
- result = __builtin_mve_vldrwq_gather_base_wb_uv4si (*__addr, __offset);
- __addr += __offset;
+ result = __builtin_mve_vldrwq_gather_base_nowb_uv4si (*__addr, __offset);
+ *__addr = __builtin_mve_vldrwq_gather_base_wb_uv4si (*__addr, __offset);
return result;
}
__arm_vldrwq_gather_base_wb_z_s32 (uint32x4_t * __addr, const int __offset, mve_pred16_t __p)
{
int32x4_t
- result = __builtin_mve_vldrwq_gather_base_wb_z_sv4si (*__addr, __offset, __p);
- __addr += __offset;
+ result = __builtin_mve_vldrwq_gather_base_nowb_z_sv4si (*__addr, __offset, __p);
+ *__addr = __builtin_mve_vldrwq_gather_base_wb_z_sv4si (*__addr, __offset, __p);
return result;
}
__arm_vldrwq_gather_base_wb_z_u32 (uint32x4_t * __addr, const int __offset, mve_pred16_t __p)
{
uint32x4_t
- result = __builtin_mve_vldrwq_gather_base_wb_z_uv4si (*__addr, __offset, __p);
- __addr += __offset;
+ result = __builtin_mve_vldrwq_gather_base_nowb_z_uv4si (*__addr, __offset, __p);
+ *__addr = __builtin_mve_vldrwq_gather_base_wb_z_uv4si (*__addr, __offset, __p);
return result;
}
__arm_vldrwq_gather_base_wb_f32 (uint32x4_t * __addr, const int __offset)
{
float32x4_t
- result = __builtin_mve_vldrwq_gather_base_wb_fv4sf (*__addr, __offset);
- __addr += __offset;
+ result = __builtin_mve_vldrwq_gather_base_nowb_fv4sf (*__addr, __offset);
+ *__addr = __builtin_mve_vldrwq_gather_base_wb_fv4sf (*__addr, __offset);
return result;
}
__arm_vldrwq_gather_base_wb_z_f32 (uint32x4_t * __addr, const int __offset, mve_pred16_t __p)
{
float32x4_t
- result = __builtin_mve_vldrwq_gather_base_wb_z_fv4sf (*__addr, __offset, __p);
- __addr += __offset;
+ result = __builtin_mve_vldrwq_gather_base_nowb_z_fv4sf (*__addr, __offset, __p);
+ *__addr = __builtin_mve_vldrwq_gather_base_wb_z_fv4sf (*__addr, __offset, __p);
return result;
}
VAR1 (STRSBWBS_P, vstrwq_scatter_base_wb_p_s, v4si)
VAR1 (STRSBWBS_P, vstrwq_scatter_base_wb_p_f, v4sf)
VAR1 (STRSBWBS_P, vstrdq_scatter_base_wb_p_s, v2di)
-VAR1 (LDRGBWBU_Z, vldrwq_gather_base_wb_z_u, v4si)
-VAR1 (LDRGBWBU_Z, vldrdq_gather_base_wb_z_u, v2di)
-VAR1 (LDRGBWBU, vldrwq_gather_base_wb_u, v4si)
-VAR1 (LDRGBWBU, vldrdq_gather_base_wb_u, v2di)
-VAR1 (LDRGBWBS_Z, vldrwq_gather_base_wb_z_s, v4si)
-VAR1 (LDRGBWBS_Z, vldrwq_gather_base_wb_z_f, v4sf)
-VAR1 (LDRGBWBS_Z, vldrdq_gather_base_wb_z_s, v2di)
-VAR1 (LDRGBWBS, vldrwq_gather_base_wb_s, v4si)
-VAR1 (LDRGBWBS, vldrwq_gather_base_wb_f, v4sf)
-VAR1 (LDRGBWBS, vldrdq_gather_base_wb_s, v2di)
+VAR1 (LDRGBWBU_Z, vldrwq_gather_base_nowb_z_u, v4si)
+VAR1 (LDRGBWBU_Z, vldrdq_gather_base_nowb_z_u, v2di)
+VAR1 (LDRGBWBU, vldrwq_gather_base_nowb_u, v4si)
+VAR1 (LDRGBWBU, vldrdq_gather_base_nowb_u, v2di)
+VAR1 (LDRGBWBS_Z, vldrwq_gather_base_nowb_z_s, v4si)
+VAR1 (LDRGBWBS_Z, vldrwq_gather_base_nowb_z_f, v4sf)
+VAR1 (LDRGBWBS_Z, vldrdq_gather_base_nowb_z_s, v2di)
+VAR1 (LDRGBWBS, vldrwq_gather_base_nowb_s, v4si)
+VAR1 (LDRGBWBS, vldrwq_gather_base_nowb_f, v4sf)
+VAR1 (LDRGBWBS, vldrdq_gather_base_nowb_s, v2di)
+VAR1 (LDRGBWBXU_Z, vldrdq_gather_base_wb_z_s, v2di)
+VAR1 (LDRGBWBXU_Z, vldrdq_gather_base_wb_z_u, v2di)
+VAR1 (LDRGBWBXU, vldrdq_gather_base_wb_s, v2di)
+VAR1 (LDRGBWBXU, vldrdq_gather_base_wb_u, v2di)
+VAR1 (LDRGBWBXU_Z, vldrwq_gather_base_wb_z_s, v4si)
+VAR1 (LDRGBWBXU_Z, vldrwq_gather_base_wb_z_f, v4sf)
+VAR1 (LDRGBWBXU_Z, vldrwq_gather_base_wb_z_u, v4si)
+VAR1 (LDRGBWBXU, vldrwq_gather_base_wb_s, v4si)
+VAR1 (LDRGBWBXU, vldrwq_gather_base_wb_f, v4sf)
+VAR1 (LDRGBWBXU, vldrwq_gather_base_wb_u, v4si)
VAR1 (BINOP_NONE_NONE_NONE, vadciq_s, v4si)
VAR1 (BINOP_UNONE_UNONE_UNONE, vadciq_u, v4si)
VAR1 (BINOP_NONE_NONE_NONE, vadcq_s, v4si)
(match_operand:SI 2 "mve_vldrd_immediate")
(unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
"TARGET_HAVE_MVE"
+{
+ rtx ignore_result = gen_reg_rtx (V4SImode);
+ emit_insn (
+ gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (ignore_result, operands[0],
+ operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "mve_vldrwq_gather_base_nowb_<supf>v4si"
+ [(match_operand:V4SI 0 "s_register_operand")
+ (match_operand:V4SI 1 "s_register_operand")
+ (match_operand:SI 2 "mve_vldrd_immediate")
+ (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
+ "TARGET_HAVE_MVE"
{
rtx ignore_wb = gen_reg_rtx (V4SImode);
emit_insn (
(match_operand:HI 3 "vpr_register_operand")
(unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
"TARGET_HAVE_MVE"
+{
+ rtx ignore_result = gen_reg_rtx (V4SImode);
+ emit_insn (
+ gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (ignore_result, operands[0],
+ operands[1], operands[2],
+ operands[3]));
+ DONE;
+})
+(define_expand "mve_vldrwq_gather_base_nowb_z_<supf>v4si"
+ [(match_operand:V4SI 0 "s_register_operand")
+ (match_operand:V4SI 1 "s_register_operand")
+ (match_operand:SI 2 "mve_vldrd_immediate")
+ (match_operand:HI 3 "vpr_register_operand")
+ (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
+ "TARGET_HAVE_MVE"
{
rtx ignore_wb = gen_reg_rtx (V4SImode);
emit_insn (
ops[0] = operands[0];
ops[1] = operands[2];
ops[2] = operands[3];
- output_asm_insn ("vpst\;\tvldrwt.u32\t%q0, [%q1, %2]!",ops);
+ output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops);
return "";
}
[(set_attr "length" "8")])
(define_expand "mve_vldrwq_gather_base_wb_fv4sf"
+ [(match_operand:V4SI 0 "s_register_operand")
+ (match_operand:V4SI 1 "s_register_operand")
+ (match_operand:SI 2 "mve_vldrd_immediate")
+ (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+{
+ rtx ignore_result = gen_reg_rtx (V4SFmode);
+ emit_insn (
+ gen_mve_vldrwq_gather_base_wb_fv4sf_insn (ignore_result, operands[0],
+ operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "mve_vldrwq_gather_base_nowb_fv4sf"
[(match_operand:V4SF 0 "s_register_operand")
(match_operand:V4SI 1 "s_register_operand")
(match_operand:SI 2 "mve_vldrd_immediate")
[(set_attr "length" "4")])
(define_expand "mve_vldrwq_gather_base_wb_z_fv4sf"
+ [(match_operand:V4SI 0 "s_register_operand")
+ (match_operand:V4SI 1 "s_register_operand")
+ (match_operand:SI 2 "mve_vldrd_immediate")
+ (match_operand:HI 3 "vpr_register_operand")
+ (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
+ "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
+{
+ rtx ignore_result = gen_reg_rtx (V4SFmode);
+ emit_insn (
+ gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (ignore_result, operands[0],
+ operands[1], operands[2],
+ operands[3]));
+ DONE;
+})
+
+(define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf"
[(match_operand:V4SF 0 "s_register_operand")
(match_operand:V4SI 1 "s_register_operand")
(match_operand:SI 2 "mve_vldrd_immediate")
ops[0] = operands[0];
ops[1] = operands[2];
ops[2] = operands[3];
- output_asm_insn ("vpst\;\tvldrwt.u32\t%q0, [%q1, %2]!",ops);
+ output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops);
return "";
}
[(set_attr "length" "8")])
(match_operand:SI 2 "mve_vldrd_immediate")
(unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
"TARGET_HAVE_MVE"
+{
+ rtx ignore_result = gen_reg_rtx (V2DImode);
+ emit_insn (
+ gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (ignore_result, operands[0],
+ operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "mve_vldrdq_gather_base_nowb_<supf>v2di"
+ [(match_operand:V2DI 0 "s_register_operand")
+ (match_operand:V2DI 1 "s_register_operand")
+ (match_operand:SI 2 "mve_vldrd_immediate")
+ (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
+ "TARGET_HAVE_MVE"
{
rtx ignore_wb = gen_reg_rtx (V2DImode);
emit_insn (
DONE;
})
+
;;
;; [vldrdq_gather_base_wb_s vldrdq_gather_base_wb_u]
;;
(match_operand:HI 3 "vpr_register_operand")
(unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
"TARGET_HAVE_MVE"
+{
+ rtx ignore_result = gen_reg_rtx (V2DImode);
+ emit_insn (
+ gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (ignore_result, operands[0],
+ operands[1], operands[2],
+ operands[3]));
+ DONE;
+})
+
+(define_expand "mve_vldrdq_gather_base_nowb_z_<supf>v2di"
+ [(match_operand:V2DI 0 "s_register_operand")
+ (match_operand:V2DI 1 "s_register_operand")
+ (match_operand:SI 2 "mve_vldrd_immediate")
+ (match_operand:HI 3 "vpr_register_operand")
+ (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
+ "TARGET_HAVE_MVE"
{
rtx ignore_wb = gen_reg_rtx (V2DImode);
emit_insn (
ops[0] = operands[0];
ops[1] = operands[2];
ops[2] = operands[3];
- output_asm_insn ("vpst\;\tvldrdt.u64\t%q0, [%q1, %2]!",ops);
+ output_asm_insn ("vpst\;vldrdt.u64\t%q0, [%q1, %2]!",ops);
return "";
}
[(set_attr "length" "8")])
+2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ PR target/94317
+ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Modify.
+ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.
+
2020-04-02 Tobias Burnus <tobias@codesourcery.com>
PR fortran/93522
return vldrdq_gather_base_wb_s64 (addr, 8);
}
-/* { dg-final { scan-assembler "vldrd.64" } } */
+/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
+/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
return vldrdq_gather_base_wb_u64 (addr, 8);
}
-/* { dg-final { scan-assembler "vldrd.64" } } */
+/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
+/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
return vldrdq_gather_base_wb_z_s64 (addr, 1016, p);
}
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
+/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*$" } } */
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
return vldrdq_gather_base_wb_z_u64 (addr, 8, p);
}
-/* { dg-final { scan-assembler "vldrdt.u64" } } */
+/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
+/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
return vldrwq_gather_base_wb_f32 (addr, 8);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
+/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
return vldrwq_gather_base_wb_s32 (addr, 8);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
+/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
return vldrwq_gather_base_wb_u32 (addr, 8);
}
-/* { dg-final { scan-assembler "vldrw.u32" } } */
+/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
+/* { dg-final { scan-assembler "vldrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
return vldrwq_gather_base_wb_z_f32 (addr, 8, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
+/* { dg-final { scan-assembler "vmsr\tP0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
return vldrwq_gather_base_wb_z_s32 (addr, 8, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
+/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
return vldrwq_gather_base_wb_z_u32 (addr, 8, p);
}
-/* { dg-final { scan-assembler "vldrwt.u32" } } */
+/* { dg-final { scan-assembler "vldrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
+/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vstrb.8 q\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */
projects / gcc.git / commitdiff