debug print qemu and simulator LR
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 27 May 2021 17:37:38 +0000 (18:37 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 27 May 2021 17:37:38 +0000 (18:37 +0100)
src/openpower/decoder/isa/pypowersim.py

index 5a4d3e6d6de51c5a9a3c95624e6fc4223365f118..159c7c56931a1449f7509cd30b3e338e6bf6e59a 100644 (file)
@@ -93,13 +93,16 @@ def qemu_register_compare(sim, q, regs, fprs):
     sim_cr = sim.cr.value
     sim_pc = sim.pc.CIA.value
     sim_xer = sim.spr['XER'].value
+    sim_lr = sim.spr['LR'].value
     print("qemu pc", hex(qpc))
     print("qemu cr", hex(qcr))
+    print("qemu lr", bin(qlr))
     print("qemu xer", bin(qxer))
     print("sim nia", hex(sim.pc.NIA.value))
     print("sim pc", hex(sim.pc.CIA.value))
     print("sim cr", hex(sim_cr))
     print("sim xer", hex(sim_xer))
+    print("sim lr", hex(sim_lr))
     #self.assertEqual(qpc, sim_pc)
     for reg in regs:
         qemu_val = q.get_gpr(reg)