x86: Add pmovzx/pmovsx patterns with memory operands

Many x86 pmovzx/pmovsx instructions with memory operands are modeled in
a wrong way.  For example:

(define_insn "sse4_1_<code>v8qiv8hi2<mask_name>"
  [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
    (any_extend:V8HI
      (vec_select:V8QI
        (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm")
        (parallel [(const_int 0) (const_int 1)
               (const_int 2) (const_int 3)
               (const_int 4) (const_int 5)
               (const_int 6) (const_int 7)]))))]

should be defind for memory operands as:

(define_insn "sse4_1_<code>v8qiv8hi2<mask_name>"
  [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
    (any_extend:V8HI
      (match_operand:V8QI "memory_operand" "m,m,m")))]

This patch updates them to

(define_insn "sse4_1_<code>v8qiv8hi2<mask_name>"
  [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
	(any_extend:V8HI
	  (vec_select:V8QI
	    (match_operand:V16QI 1 "register_operand" "Yr,*x,v")
	    (parallel [(const_int 0) (const_int 1)
		       (const_int 2) (const_int 3)
		       (const_int 4) (const_int 5)
		       (const_int 6) (const_int 7)]))))]

(define_insn "*sse4_1_<code>v8qiv8hi2<mask_name>_1"
  [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
	(any_extend:V8HI
	  (match_operand:V8QI "subreg_memory_operand" "m,m,m")))]

with a splitter:

(define_insn_and_split "*sse4_1_<code>v8qiv8hi2<mask_name>_2"
  [(set (match_operand:V8HI 0 "register_operand")
        (any_extend:V8HI
          (vec_select:V8QI
            (subreg:V16QI
              (vec_concat:V2DI
                (match_operand:DI 1 "memory_operand")
                (const_int 0)) 0)
            (parallel [(const_int 0) (const_int 1)
                       (const_int 2) (const_int 3)
                       (const_int 4) (const_int 5)
                       (const_int 6) (const_int 7)]))))]
  "TARGET_SSE4_1
   && <mask_avx512bw_condition>
   && <mask_avx512vl_condition>
  "&& can_create_pseudo_p ()"
  "#"
  "&& 1"
  [(set (match_dup 0)
        (any_extend:V8HI (match_dup 1)))]
  "operands[1] = adjust_address_nv (operands[1], V8QImode, 0);")

This patch requires updating apply_subst_iterator to handle
define_insn_and_split.

gcc/

	PR target/87317
	* config/i386/sse.md (sse4_1_<code>v8qiv8hi2<mask_name>): Replace
	nonimmediate_operand with register_operand.
	(avx2_<code>v8qiv8si2<mask_name>): Likewise.
	(sse4_1_<code>v4qiv4si2<mask_name>): Likewise.
	(sse4_1_<code>v4hiv4si2<mask_name>): Likewise.
	(sse4_1_<code>v2qiv2di2<mask_name>): Likewise.
	(avx512f_<code>v8qiv8di2<mask_name>): Likewise.
	(avx2_<code>v4qiv4di2<mask_name>): Likewise.
	(avx2_<code>v4hiv4di2<mask_name>): Likewise.
	(sse4_1_<code>v2hiv2di2<mask_name>): Likewise.
	(sse4_1_<code>v2siv2di2<mask_name>): Likewise.
	(*sse4_1_<code>v8qiv8hi2<mask_name>_1): New pattern.
	(*sse4_1_<code>v8qiv8hi2<mask_name>_2): Likewise.
	(*avx2_<code>v8qiv8si2<mask_name>_1): Likewise.
	(*avx2_<code>v8qiv8si2<mask_name>_2): Likewise.
	(*sse4_1_<code>v4qiv4si2<mask_name>_1): Likewise.
	(*sse4_1_<code>v4qiv4si2<mask_name>_2): Likewise.
	(*sse4_1_<code>v4hiv4si2<mask_name>_1): Likewise.
	(*sse4_1_<code>v4hiv4si2<mask_name>_2): Likewise.
	(*avx512f_<code>v8qiv8di2<mask_name>_1): Likewise.
	(*avx512f_<code>v8qiv8di2<mask_name>_2): Likewise.
	(*avx2_<code>v4qiv4di2<mask_name>_1): Likewise.
	(*avx2_<code>v4qiv4di2<mask_name>_2): Likewise.
	(*avx2_<code>v4hiv4di2<mask_name>_1): Likewise.
	(*avx2_<code>v4hiv4di2<mask_name>_2): Likewise.
	(*sse4_1_<code>v2hiv2di2<mask_name>_1): Likewise.
	(*sse4_1_<code>v2hiv2di2<mask_name>_2): Likewise.
	(*sse4_1_<code>v2siv2di2<mask_name>_1): Likewise.
	(*sse4_1_<code>v2siv2di2<mask_name>_2): Likewise.

gcc/testsuite/

	PR target/87317
	* gcc.target/i386/pr87317-1.c: New file.
	* gcc.target/i386/pr87317-2.c: Likewise.
	* gcc.target/i386/pr87317-3.c: Likewise.
	* gcc.target/i386/pr87317-4.c: Likewise.
	* gcc.target/i386/pr87317-5.c: Likewise.
	* gcc.target/i386/pr87317-6.c: Likewise.
	* gcc.target/i386/pr87317-7.c: Likewise.
	* gcc.target/i386/pr87317-8.c: Likewise.
	* gcc.target/i386/pr87317-9.c: Likewise.
	* gcc.target/i386/pr87317-10.c: Likewise.
	* gcc.target/i386/pr87317-11.c: Likewise.
	* gcc.target/i386/pr87317-12.c: Likewise.
	* gcc.target/i386/pr87317-13.c: Likewise.

From-SVN: r266342

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2728ccbe671d143207bb92ffd991ce3c85e3f8fa..692f3fb1961576316fd558a15bd49b56d32e0190 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,36 @@
+2018-11-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/87317
+       * config/i386/sse.md (sse4_1_<code>v8qiv8hi2<mask_name>): Replace
+       nonimmediate_operand with register_operand.
+       (avx2_<code>v8qiv8si2<mask_name>): Likewise.
+       (sse4_1_<code>v4qiv4si2<mask_name>): Likewise.
+       (sse4_1_<code>v4hiv4si2<mask_name>): Likewise.
+       (sse4_1_<code>v2qiv2di2<mask_name>): Likewise.
+       (avx512f_<code>v8qiv8di2<mask_name>): Likewise.
+       (avx2_<code>v4qiv4di2<mask_name>): Likewise.
+       (avx2_<code>v4hiv4di2<mask_name>): Likewise.
+       (sse4_1_<code>v2hiv2di2<mask_name>): Likewise.
+       (sse4_1_<code>v2siv2di2<mask_name>): Likewise.
+       (*sse4_1_<code>v8qiv8hi2<mask_name>_1): New pattern.
+       (*sse4_1_<code>v8qiv8hi2<mask_name>_2): Likewise.
+       (*avx2_<code>v8qiv8si2<mask_name>_1): Likewise.
+       (*avx2_<code>v8qiv8si2<mask_name>_2): Likewise.
+       (*sse4_1_<code>v4qiv4si2<mask_name>_1): Likewise.
+       (*sse4_1_<code>v4qiv4si2<mask_name>_2): Likewise.
+       (*sse4_1_<code>v4hiv4si2<mask_name>_1): Likewise.
+       (*sse4_1_<code>v4hiv4si2<mask_name>_2): Likewise.
+       (*avx512f_<code>v8qiv8di2<mask_name>_1): Likewise.
+       (*avx512f_<code>v8qiv8di2<mask_name>_2): Likewise.
+       (*avx2_<code>v4qiv4di2<mask_name>_1): Likewise.
+       (*avx2_<code>v4qiv4di2<mask_name>_2): Likewise.
+       (*avx2_<code>v4hiv4di2<mask_name>_1): Likewise.
+       (*avx2_<code>v4hiv4di2<mask_name>_2): Likewise.
+       (*sse4_1_<code>v2hiv2di2<mask_name>_1): Likewise.
+       (*sse4_1_<code>v2hiv2di2<mask_name>_2): Likewise.
+       (*sse4_1_<code>v2siv2di2<mask_name>_1): Likewise.
+       (*sse4_1_<code>v2siv2di2<mask_name>_2): Likewise.
+
 2018-11-21  H.J. Lu  <hongjiu.lu@intel.com>
 
        * read-rtl.c (apply_subst_iterator): Handle define_split and

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 18685de9131f29b093a1dd37b8b84190e3f72118..e2d2b452340382634f11a6be964755cb477640ff 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15839,19 +15839,51 @@
   [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
        (any_extend:V8HI
          (vec_select:V8QI
-           (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm")
+           (match_operand:V16QI 1 "register_operand" "Yr,*x,v")
            (parallel [(const_int 0) (const_int 1)
                       (const_int 2) (const_int 3)
                       (const_int 4) (const_int 5)
                       (const_int 6) (const_int 7)]))))]
   "TARGET_SSE4_1 && <mask_avx512bw_condition> && <mask_avx512vl_condition>"
-  "%vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
+  "%vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
    (set_attr "mode" "TI")])
 
+(define_insn "*sse4_1_<code>v8qiv8hi2<mask_name>_1"
+  [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
+       (any_extend:V8HI
+         (match_operand:V8QI 1 "memory_operand" "m,m,m")))]
+  "TARGET_SSE4_1 && <mask_avx512bw_condition> && <mask_avx512vl_condition>"
+  "%vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "isa" "noavx,noavx,avx")
+   (set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,orig,maybe_evex")
+   (set_attr "mode" "TI")])
+
+(define_insn_and_split "*sse4_1_<code>v8qiv8hi2<mask_name>_2"
+  [(set (match_operand:V8HI 0 "register_operand")
+       (any_extend:V8HI
+         (vec_select:V8QI
+           (subreg:V16QI
+             (vec_concat:V2DI
+               (match_operand:DI 1 "memory_operand")
+               (const_int 0)) 0)
+           (parallel [(const_int 0) (const_int 1)
+                      (const_int 2) (const_int 3)
+                      (const_int 4) (const_int 5)
+                      (const_int 6) (const_int 7)]))))]
+  "TARGET_SSE4_1 && <mask_avx512bw_condition> && <mask_avx512vl_condition>
+   && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+       (any_extend:V8HI (match_dup 1)))]
+  "operands[1] = adjust_address_nv (operands[1], V8QImode, 0);")
+
 (define_insn "<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>"
   [(set (match_operand:V16SI 0 "register_operand" "=v")
        (any_extend:V16SI
@@ -15866,33 +15898,98 @@
   [(set (match_operand:V8SI 0 "register_operand" "=v")
        (any_extend:V8SI
          (vec_select:V8QI
-           (match_operand:V16QI 1 "nonimmediate_operand" "vm")
+           (match_operand:V16QI 1 "register_operand" "v")
            (parallel [(const_int 0) (const_int 1)
                       (const_int 2) (const_int 3)
                       (const_int 4) (const_int 5)
                       (const_int 6) (const_int 7)]))))]
   "TARGET_AVX2 && <mask_avx512vl_condition>"
-  "vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
+  "vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "OI")])
 
+(define_insn "*avx2_<code>v8qiv8si2<mask_name>_1"
+  [(set (match_operand:V8SI 0 "register_operand" "=v")
+       (any_extend:V8SI
+         (match_operand:V8QI 1 "memory_operand" "m")))]
+  "TARGET_AVX2 && <mask_avx512vl_condition>"
+  "%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "maybe_evex")
+   (set_attr "mode" "OI")])
+
+(define_insn_and_split "*avx2_<code>v8qiv8si2<mask_name>_2"
+  [(set (match_operand:V8SI 0 "register_operand")
+       (any_extend:V8SI
+         (vec_select:V8QI
+           (subreg:V16QI
+             (vec_concat:V2DI
+               (match_operand:DI 1 "memory_operand")
+               (const_int 0)) 0)
+           (parallel [(const_int 0) (const_int 1)
+                      (const_int 2) (const_int 3)
+                      (const_int 4) (const_int 5)
+                      (const_int 6) (const_int 7)]))))]
+  "TARGET_AVX2 && <mask_avx512vl_condition>
+   && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+       (any_extend:V8SI (match_dup 1)))]
+  "operands[1] = adjust_address_nv (operands[1], V8QImode, 0);")
+
 (define_insn "sse4_1_<code>v4qiv4si2<mask_name>"
   [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v")
        (any_extend:V4SI
          (vec_select:V4QI
-           (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm")
+           (match_operand:V16QI 1 "register_operand" "Yr,*x,v")
            (parallel [(const_int 0) (const_int 1)
                       (const_int 2) (const_int 3)]))))]
   "TARGET_SSE4_1 && <mask_avx512vl_condition>"
-  "%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %k1}"
+  "%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
    (set_attr "mode" "TI")])
 
+(define_insn "*sse4_1_<code>v4qiv4si2<mask_name>_1"
+  [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v")
+       (any_extend:V4SI
+         (match_operand:V4QI 1 "memory_operand" "m,m,m")))]
+  "TARGET_SSE4_1 && <mask_avx512vl_condition>"
+  "%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "isa" "noavx,noavx,avx")
+   (set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,orig,maybe_evex")
+   (set_attr "mode" "TI")])
+
+(define_insn_and_split "*sse4_1_<code>v4qiv4si2<mask_name>_2"
+  [(set (match_operand:V4SI 0 "register_operand")
+       (any_extend:V4SI
+         (vec_select:V4QI
+           (subreg:V16QI
+             (vec_merge:V4SI
+               (vec_duplicate:V4SI
+                 (match_operand:SI 1 "memory_operand"))
+               (const_vector:V4SI
+                  [(const_int 0) (const_int 0)
+                   (const_int 0) (const_int 0)])
+               (const_int 1)) 0)
+           (parallel [(const_int 0) (const_int 1)
+                      (const_int 2) (const_int 3)]))))]
+  "TARGET_SSE4_1 && <mask_avx512vl_condition>
+   && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+       (any_extend:V4SI (match_dup 1)))]
+  "operands[1] = adjust_address_nv (operands[1], V4QImode, 0);")
+
 (define_insn "avx512f_<code>v16hiv16si2<mask_name>"
   [(set (match_operand:V16SI 0 "register_operand" "=v")
        (any_extend:V16SI
@@ -15918,54 +16015,146 @@
   [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v")
        (any_extend:V4SI
          (vec_select:V4HI
-           (match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*xm,vm")
+           (match_operand:V8HI 1 "register_operand" "Yr,*x,v")
            (parallel [(const_int 0) (const_int 1)
                       (const_int 2) (const_int 3)]))))]
   "TARGET_SSE4_1 && <mask_avx512vl_condition>"
-  "%vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
+  "%vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "isa" "noavx,noavx,avx")
+   (set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,orig,maybe_evex")
+   (set_attr "mode" "TI")])
+
+(define_insn "*sse4_1_<code>v4hiv4si2<mask_name>_1"
+  [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v")
+       (any_extend:V4SI
+         (match_operand:V4HI 1 "memory_operand" "m,m,m")))]
+  "TARGET_SSE4_1 && <mask_avx512vl_condition>"
+  "%vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
    (set_attr "mode" "TI")])
 
+(define_insn_and_split "*sse4_1_<code>v4hiv4si2<mask_name>_2"
+  [(set (match_operand:V4SI 0 "register_operand")
+       (any_extend:V4SI
+         (vec_select:V4HI
+           (subreg:V8HI
+             (vec_concat:V2DI
+               (match_operand:DI 1 "memory_operand")
+               (const_int 0)) 0)
+           (parallel [(const_int 0) (const_int 1)
+                      (const_int 2) (const_int 3)]))))]
+  "TARGET_SSE4_1 && <mask_avx512vl_condition>
+   && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+       (any_extend:V4SI (match_dup 1)))]
+  "operands[1] = adjust_address_nv (operands[1], V4HImode, 0);")
+
 (define_insn "avx512f_<code>v8qiv8di2<mask_name>"
   [(set (match_operand:V8DI 0 "register_operand" "=v")
        (any_extend:V8DI
          (vec_select:V8QI
-           (match_operand:V16QI 1 "nonimmediate_operand" "vm")
+           (match_operand:V16QI 1 "register_operand" "v")
            (parallel [(const_int 0) (const_int 1)
                       (const_int 2) (const_int 3)
                       (const_int 4) (const_int 5)
                       (const_int 6) (const_int 7)]))))]
   "TARGET_AVX512F"
-  "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %k1}"
+  "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "type" "ssemov")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "XI")])
+
+(define_insn "*avx512f_<code>v8qiv8di2<mask_name>_1"
+  [(set (match_operand:V8DI 0 "register_operand" "=v")
+       (any_extend:V8DI
+         (match_operand:V8QI 1 "memory_operand" "m")))]
+  "TARGET_AVX512F"
+  "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix" "evex")
    (set_attr "mode" "XI")])
 
+(define_insn_and_split "*avx512f_<code>v8qiv8di2<mask_name>_2"
+  [(set (match_operand:V8DI 0 "register_operand")
+       (any_extend:V8DI
+         (vec_select:V8QI
+           (subreg:V16QI
+             (vec_concat:V2DI
+               (match_operand:DI 1 "memory_operand")
+               (const_int 0)) 0)
+           (parallel [(const_int 0) (const_int 1)
+                      (const_int 2) (const_int 3)
+                      (const_int 4) (const_int 5)
+                      (const_int 6) (const_int 7)]))))]
+  "TARGET_AVX512F && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+       (any_extend:V8DI (match_dup 1)))]
+  "operands[1] = adjust_address_nv (operands[1], V8QImode, 0);")
+
 (define_insn "avx2_<code>v4qiv4di2<mask_name>"
   [(set (match_operand:V4DI 0 "register_operand" "=v")
        (any_extend:V4DI
          (vec_select:V4QI
-           (match_operand:V16QI 1 "nonimmediate_operand" "vm")
+           (match_operand:V16QI 1 "register_operand" "v")
            (parallel [(const_int 0) (const_int 1)
                       (const_int 2) (const_int 3)]))))]
   "TARGET_AVX2 && <mask_avx512vl_condition>"
-  "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %k1}"
+  "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "OI")])
 
+(define_insn "*avx2_<code>v4qiv4di2<mask_name>_1"
+  [(set (match_operand:V4DI 0 "register_operand" "=v")
+       (any_extend:V4DI
+         (match_operand:V4QI 1 "memory_operand" "m")))]
+  "TARGET_AVX2 && <mask_avx512vl_condition>"
+  "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "maybe_evex")
+   (set_attr "mode" "OI")])
+
+(define_insn_and_split "*avx2_<code>v4qiv4di2<mask_name>_2"
+  [(set (match_operand:V4DI 0 "register_operand")
+       (any_extend:V4DI
+         (vec_select:V4QI
+           (subreg:V16QI
+             (vec_merge:V4SI
+               (vec_duplicate:V4SI
+                 (match_operand:SI 1 "memory_operand"))
+               (const_vector:V4SI
+                  [(const_int 0) (const_int 0)
+                   (const_int 0) (const_int 0)])
+               (const_int 1)) 0)
+           (parallel [(const_int 0) (const_int 1)
+                      (const_int 2) (const_int 3)]))))]
+  "TARGET_AVX2 && <mask_avx512vl_condition>
+   && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+       (any_extend:V4DI (match_dup 1)))]
+  "operands[1] = adjust_address_nv (operands[1], V4QImode, 0);")
+
 (define_insn "sse4_1_<code>v2qiv2di2<mask_name>"
   [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v")
        (any_extend:V2DI
          (vec_select:V2QI
-           (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm")
+           (match_operand:V16QI 1 "register_operand" "Yr,*x,v")
            (parallel [(const_int 0) (const_int 1)]))))]
   "TARGET_SSE4_1 && <mask_avx512vl_condition>"
-  "%vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %w1}"
+  "%vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
@@ -15986,30 +16175,92 @@
   [(set (match_operand:V4DI 0 "register_operand" "=v")
        (any_extend:V4DI
          (vec_select:V4HI
-           (match_operand:V8HI 1 "nonimmediate_operand" "vm")
+           (match_operand:V8HI 1 "register_operand" "v")
            (parallel [(const_int 0) (const_int 1)
                       (const_int 2) (const_int 3)]))))]
   "TARGET_AVX2 && <mask_avx512vl_condition>"
-  "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
+  "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "maybe_evex")
+   (set_attr "mode" "OI")])
+
+(define_insn "*avx2_<code>v4hiv4di2<mask_name>_1"
+  [(set (match_operand:V4DI 0 "register_operand" "=v")
+       (any_extend:V4DI
+         (match_operand:V4HI 1 "memory_operand" "m")))]
+  "TARGET_AVX2 && <mask_avx512vl_condition>"
+  "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "OI")])
 
+(define_insn_and_split "*avx2_<code>v4hiv4di2<mask_name>_2"
+  [(set (match_operand:V4DI 0 "register_operand")
+       (any_extend:V4DI
+         (vec_select:V4HI
+           (subreg:V8HI
+             (vec_concat:V2DI
+               (match_operand:DI 1 "memory_operand")
+               (const_int 0)) 0)
+           (parallel [(const_int 0) (const_int 1)
+                      (const_int 2) (const_int 3)]))))]
+  "TARGET_AVX2 && <mask_avx512vl_condition>
+   && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+       (any_extend:V4DI (match_dup 1)))]
+  "operands[1] = adjust_address_nv (operands[1], V4HImode, 0);")
+
 (define_insn "sse4_1_<code>v2hiv2di2<mask_name>"
   [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v")
        (any_extend:V2DI
          (vec_select:V2HI
-           (match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*xm,vm")
+           (match_operand:V8HI 1 "register_operand" "Yr,*x,v")
            (parallel [(const_int 0) (const_int 1)]))))]
   "TARGET_SSE4_1 && <mask_avx512vl_condition>"
-  "%vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %k1}"
+  "%vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "isa" "noavx,noavx,avx")
+   (set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,orig,maybe_evex")
+   (set_attr "mode" "TI")])
+
+(define_insn "*sse4_1_<code>v2hiv2di2<mask_name>_1"
+  [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v")
+       (any_extend:V2DI
+         (match_operand:V2HI 1 "memory_operand" "m,m,m")))]
+  "TARGET_SSE4_1 && <mask_avx512vl_condition>"
+  "%vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
    (set_attr "mode" "TI")])
 
+(define_insn_and_split "*sse4_1_<code>v2hiv2di2<mask_name>_2"
+  [(set (match_operand:V2DI 0 "register_operand")
+       (any_extend:V2DI
+         (vec_select:V2HI
+           (subreg:V8HI
+             (vec_merge:V4SI
+               (vec_duplicate:V4SI
+                 (match_operand:SI 1 "memory_operand"))
+               (const_vector:V4SI
+                  [(const_int 0) (const_int 0)
+                   (const_int 0) (const_int 0)])
+               (const_int 1)) 0)
+           (parallel [(const_int 0) (const_int 1)]))))]
+  "TARGET_SSE4_1 && <mask_avx512vl_condition>
+   && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+       (any_extend:V2DI (match_dup 1)))]
+  "operands[1] = adjust_address_nv (operands[1], V2HImode, 0);")
+
 (define_insn "avx512f_<code>v8siv8di2<mask_name>"
   [(set (match_operand:V8DI 0 "register_operand" "=v")
        (any_extend:V8DI
@@ -16035,16 +16286,45 @@
   [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v")
        (any_extend:V2DI
          (vec_select:V2SI
-           (match_operand:V4SI 1 "nonimmediate_operand" "Yrm,*xm,vm")
+           (match_operand:V4SI 1 "register_operand" "Yr,*x,v")
            (parallel [(const_int 0) (const_int 1)]))))]
   "TARGET_SSE4_1 && <mask_avx512vl_condition>"
-  "%vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
+  "%vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+  [(set_attr "isa" "noavx,noavx,avx")
+   (set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,orig,maybe_evex")
+   (set_attr "mode" "TI")])
+
+(define_insn "*sse4_1_<code>v2siv2di2<mask_name>_1"
+  [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v")
+       (any_extend:V2DI
+         (match_operand:V2SI 1 "memory_operand" "m,m,m")))]
+  "TARGET_SSE4_1 && <mask_avx512vl_condition>"
+  "%vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "isa" "noavx,noavx,avx")
    (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "orig,orig,maybe_evex")
    (set_attr "mode" "TI")])
 
+(define_insn_and_split "*sse4_1_<code>v2siv2di2<mask_name>_2"
+  [(set (match_operand:V2DI 0 "register_operand")
+       (any_extend:V2DI
+         (vec_select:V2SI
+           (subreg:V4SI
+             (vec_concat:V2DI
+               (match_operand:DI 1 "memory_operand")
+               (const_int 0)) 0)
+           (parallel [(const_int 0) (const_int 1)]))))]
+  "TARGET_SSE4_1 && <mask_avx512vl_condition>
+   && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+       (any_extend:V2DI (match_dup 1)))]
+  "operands[1] = adjust_address_nv (operands[1], V2SImode, 0);")
+
 ;; ptestps/ptestpd are very similar to comiss and ucomiss when
 ;; setting FLAGS_REG. But it is not a really compare instruction.
 (define_insn "avx_vtest<ssemodesuffix><avxsizesuffix>"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 855cc5963b7513b7afe8cdd8a3631c72d94178c9..548959361b8ed6d118528ed54dea2eeaedf1678a 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,20 @@
+2018-11-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/87317
+       * gcc.target/i386/pr87317-1.c: New file.
+       * gcc.target/i386/pr87317-2.c: Likewise.
+       * gcc.target/i386/pr87317-3.c: Likewise.
+       * gcc.target/i386/pr87317-4.c: Likewise.
+       * gcc.target/i386/pr87317-5.c: Likewise.
+       * gcc.target/i386/pr87317-6.c: Likewise.
+       * gcc.target/i386/pr87317-7.c: Likewise.
+       * gcc.target/i386/pr87317-8.c: Likewise.
+       * gcc.target/i386/pr87317-9.c: Likewise.
+       * gcc.target/i386/pr87317-10.c: Likewise.
+       * gcc.target/i386/pr87317-11.c: Likewise.
+       * gcc.target/i386/pr87317-12.c: Likewise.
+       * gcc.target/i386/pr87317-13.c: Likewise.
+
 2018-11-21  Tom de Vries  <tdevries@suse.de>
 
        PR driver/79855

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-1.c b/gcc/testsuite/gcc.target/i386/pr87317-1.c
new file mode 100644 (file)
index 0000000..ec6b11d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovzxbw" 1 } } */
+/* { dg-final { scan-assembler-not "vmovq" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i data = _mm_cvtsi64_si128(*(long long int*)ptr);
+  data = _mm_cvtepu8_epi16(data);
+  _mm_storeu_si128((__m128i*)dst, data);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-10.c b/gcc/testsuite/gcc.target/i386/pr87317-10.c
new file mode 100644 (file)
index 0000000..ea9a7a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-10.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovzxbd" 1 } } */
+/* { dg-final { scan-assembler-not "vmovq" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i y = _mm_cvtsi64_si128(*(long long int*)ptr);
+  __m256i z = _mm256_cvtepu8_epi32 (y);
+  _mm256_storeu_si256((__m256i*)dst, z);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-11.c b/gcc/testsuite/gcc.target/i386/pr87317-11.c
new file mode 100644 (file)
index 0000000..13f0c23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-11.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovzxwq" 1 } } */
+/* { dg-final { scan-assembler-not "vmovq" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i y = _mm_cvtsi64_si128(*(long long int*)ptr);
+  __m256i z = _mm256_cvtepu16_epi64 (y);
+  _mm256_storeu_si256((__m256i*)dst, z);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-12.c b/gcc/testsuite/gcc.target/i386/pr87317-12.c
new file mode 100644 (file)
index 0000000..1090966
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-12.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovsxwq" 1 } } */
+
+#include <immintrin.h>
+
+#define MAX 4
+
+long long int dst[MAX];
+short src[MAX];
+
+void
+foo (void)
+{
+  int i;
+  for (i = 0; i < MAX; i += 4)
+    {
+      __m128i data = _mm_cvtsi64_si128(*(long long int*)(src + i));
+      __m256i x = _mm256_cvtepi16_epi64(data);
+      _mm256_storeu_si256((__m256i*)(dst + i), x);
+    }
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-13.c b/gcc/testsuite/gcc.target/i386/pr87317-13.c
new file mode 100644 (file)
index 0000000..d3c3def
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-13.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpmovzxbq" 1 } } */
+/* { dg-final { scan-assembler-not "vmovq" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i y = _mm_cvtsi64_si128(*(long long int*)ptr);
+  __m512i z = _mm512_cvtepu8_epi64 (y);
+  _mm512_storeu_si512((__m512i*)dst, z);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-2.c b/gcc/testsuite/gcc.target/i386/pr87317-2.c
new file mode 100644 (file)
index 0000000..e7eaaf6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovsxwd" 1 } } */
+/* { dg-final { scan-assembler-not "vmovq" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i data = _mm_cvtsi64_si128(*(long long int*)ptr);
+  data = _mm_cvtepi16_epi32(data);
+  _mm_storeu_si128((__m128i*)dst, data);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-3.c b/gcc/testsuite/gcc.target/i386/pr87317-3.c
new file mode 100644 (file)
index 0000000..f2e041a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovsxdq" 1 } } */
+/* { dg-final { scan-assembler-not "vmovq" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i data = _mm_cvtsi64_si128(*(long long int*)ptr);
+  data = _mm_cvtepi32_epi64(data);
+  _mm_storeu_si128((__m128i*)dst, data);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-4.c b/gcc/testsuite/gcc.target/i386/pr87317-4.c
new file mode 100644 (file)
index 0000000..2d4f24a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovzxbd" 1 } } */
+/* { dg-final { scan-assembler-not "vmovd" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i data = _mm_cvtsi32_si128(*(int*)ptr);
+  data = _mm_cvtepu8_epi32(data);
+  _mm_storeu_si128((__m128i*)dst, data);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-5.c b/gcc/testsuite/gcc.target/i386/pr87317-5.c
new file mode 100644 (file)
index 0000000..96f8284
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovzxwq" 1 } } */
+/* { dg-final { scan-assembler-not "vmovd" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i data = _mm_cvtsi32_si128(*(int*)ptr);
+  data = _mm_cvtepu16_epi64(data);
+  _mm_storeu_si128((__m128i*)dst, data);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-6.c b/gcc/testsuite/gcc.target/i386/pr87317-6.c
new file mode 100644 (file)
index 0000000..4fe9b11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-6.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovzxbq" 1 } } */
+/* { dg-final { scan-assembler-not "vmovq" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i y = _mm_cvtsi32_si128(*(int*)ptr);
+  __m256i z = _mm256_cvtepu8_epi64 (y);
+  _mm256_storeu_si256((__m256i*)dst, z);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-7.c b/gcc/testsuite/gcc.target/i386/pr87317-7.c
new file mode 100644 (file)
index 0000000..2c043d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-7.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovzxbd" 1 } } */
+/* { dg-final { scan-assembler-not "vmovd" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i data = _mm_cvtsi32_si128(*(int*)ptr);
+  data = _mm_cvtepu8_epi32(data);
+  _mm_storeu_si128((__m128i*)dst, data);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-8.c b/gcc/testsuite/gcc.target/i386/pr87317-8.c
new file mode 100644 (file)
index 0000000..178455f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-8.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovzxwq" 1 } } */
+/* { dg-final { scan-assembler-not "vmovq" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i data = _mm_cvtsi64_si128(*(long long int*)ptr);
+  __m256i x = _mm256_cvtepu16_epi64(data);
+  _mm256_storeu_si256((__m256i*)dst, x);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr87317-9.c b/gcc/testsuite/gcc.target/i386/pr87317-9.c
new file mode 100644 (file)
index 0000000..c5144fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr87317-9.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=haswell" } */
+/* { dg-final { scan-assembler-times "vpmovzxbd" 1 } } */
+/* { dg-final { scan-assembler-not "vmovq" } } */
+
+#include <immintrin.h>
+
+void
+f (void *dst, void *ptr)
+{
+  __m128i data = _mm_cvtsi64_si128(*(long long int*)ptr);
+  __m256i x = _mm256_cvtepu8_epi32(data);
+  _mm256_storeu_si256((__m256i*)dst, x);
+}