Split module ports, 20 per line

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6fb14d7fc8455a193fb4ca4c7c6cecbce0274453..dc5c188c0a0770cac45ae4f8ce45a0ff7f406d33 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -2062,6 +2062,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
        dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true);
        f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
        bool keep_running = true;
+       int cnt = 0;
        for (int port_id = 1; keep_running; port_id++) {
                keep_running = false;
                for (auto wire : module->wires()) {
@@ -2070,6 +2071,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
                                        f << stringf(", ");
                                f << stringf("%s", id(wire->name).c_str());
                                keep_running = true;
+                               if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
                                continue;
                        }
                }