}}, ',a');
}
default: decode BPCC {
- 0x0: fbpcc0(22, {{
+ 0x0: fbpfcc0(19, {{
if(passesFpCondition(Fsr<11:10>, COND2))
NNPC = xc->readPC() + disp;
else
handle_annul
}});
- 0x1: fbpcc1(22, {{
+ 0x1: fbpfcc1(19, {{
if(passesFpCondition(Fsr<33:32>, COND2))
NNPC = xc->readPC() + disp;
else
handle_annul
}});
- 0x2: fbpcc2(22, {{
+ 0x2: fbpfcc2(19, {{
if(passesFpCondition(Fsr<35:34>, COND2))
NNPC = xc->readPC() + disp;
else
handle_annul
}});
- 0x3: fbpcc3(22, {{
+ 0x3: fbpfcc3(19, {{
if(passesFpCondition(Fsr<37:36>, COND2))
NNPC = xc->readPC() + disp;
else
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);
0x24: mulscc({{
- int64_t resTemp, multiplicand = Rs2_or_imm13;
- int32_t multiplier = Rs1<31:0>;
int32_t savedLSB = Rs1<0:>;
- multiplier = multiplier<31:1> |
- ((Ccr<3:3> ^ Ccr<1:1>) << 32);
- if(!Y<0:>)
- multiplicand = 0;
- Rd = resTemp = multiplicand + multiplier;
+
+ //Step 1
+ int64_t multiplicand = Rs2_or_imm13;
+ //Step 2
+ int32_t partialP = Rs1<31:1> |
+ ((Ccr<3:3> ^ Ccr<1:1>) << 31);
+ //Step 3
+ int32_t added = Y<0:> ? multiplicand : 0;
+ Rd = partialP + added;
+ //Steps 4 & 5
Y = Y<31:1> | (savedLSB << 31);}},
- {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
- {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
- {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
- {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
+ {{((partialP<31:0> + added<31:0>)<32:0>)}},
+ {{partialP<31:> == added<31:> && added<31:> != Rd<31:>}},
+ {{((partialP >> 1) + (added >> 1) + (partialP & added & 0x1))<63:>}},
+ {{partialP<63:> == added<63:> && partialP<63:> != Rd<63:>}}
);
}
format IntOp
}
0x35: decode OPF{
format FpBasic{
+ 0x01: fmovs_fcc0({{
+ if(passesFpCondition(Fsr<11:10>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x02: fmovd_fcc0({{
+ if(passesFpCondition(Fsr<11:10>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x03: FpUnimpl::fmovq_fcc0();
+ 0x25: fmovrsz({{
+ if(Rs1 == 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x26: fmovrdz({{
+ if(Rs1 == 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x27: FpUnimpl::fmovrqz();
+ 0x41: fmovs_fcc1({{
+ if(passesFpCondition(Fsr<33:32>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x42: fmovd_fcc1({{
+ if(passesFpCondition(Fsr<33:32>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x43: FpUnimpl::fmovq_fcc1();
+ 0x45: fmovrslez({{
+ if(Rs1 <= 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x46: fmovrdlez({{
+ if(Rs1 <= 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x47: FpUnimpl::fmovrqlez();
0x51: fcmps({{
uint8_t fcc;
if(isnan(Frs1s) || isnan(Frs2s))
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
}});
0x57: FpUnimpl::fcmpeq();
+ 0x65: fmovrslz({{
+ if(Rs1 < 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x66: fmovrdlz({{
+ if(Rs1 < 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x67: FpUnimpl::fmovrqlz();
+ 0x81: fmovs_fcc2({{
+ if(passesFpCondition(Fsr<35:34>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x82: fmovd_fcc2({{
+ if(passesFpCondition(Fsr<35:34>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x83: FpUnimpl::fmovq_fcc2();
+ 0xA5: fmovrsnz({{
+ if(Rs1 != 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0xA6: fmovrdnz({{
+ if(Rs1 != 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0xA7: FpUnimpl::fmovrqnz();
+ 0xC1: fmovs_fcc3({{
+ if(passesFpCondition(Fsr<37:36>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0xC2: fmovd_fcc3({{
+ if(passesFpCondition(Fsr<37:36>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0xC3: FpUnimpl::fmovq_fcc3();
+ 0xC5: fmovrsgz({{
+ if(Rs1 > 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0xC6: fmovrdgz({{
+ if(Rs1 > 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0xC7: FpUnimpl::fmovrqgz();
+ 0xE5: fmovrsgez({{
+ if(Rs1 >= 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0xE6: fmovrdgez({{
+ if(Rs1 >= 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0xE7: FpUnimpl::fmovrqgez();
+ 0x101: fmovs_icc({{
+ if(passesCondition(Ccr<3:0>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x102: fmovd_icc({{
+ if(passesCondition(Ccr<3:0>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x103: FpUnimpl::fmovq_icc();
+ 0x181: fmovs_xcc({{
+ if(passesCondition(Ccr<7:4>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x182: fmovd_xcc({{
+ if(passesCondition(Ccr<7:4>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x183: FpUnimpl::fmovq_xcc();
default: FailUnimpl::fpop2();
}
}
0x04: stw({{Mem.uw = Rd.sw;}});
0x05: stb({{Mem.ub = Rd.sb;}});
0x06: sth({{Mem.uhw = Rd.shw;}});
- 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
+ 0x07: sttw({{
+ (Mem.tuw).a = RdLow<31:0>;
+ (Mem.tuw).b = RdHigh<31:0>;
+ }});
}
format Load {
0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
- 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
+ 0x17: sttwa({{
+ (Mem.tuw).a = RdLow<31:0>;
+ (Mem.tuw).b = RdHigh<31:0>;
+ }}, {{EXT_ASI}});
}
format LoadAlt {
0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
}
if(storeCond && fault == NoFault)
{
- fault = xc->write((uint%(mem_acc_size)s_t)Mem,
+ fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
if(fault == NoFault)
}
if(storeCond && fault == NoFault)
{
- fault = xc->write((uint%(mem_acc_size)s_t)Mem,
+ fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
if(fault == NoFault)
/* 125 */ SyscallDesc("recvfrom", unimplementedFunc),
/* 126 */ SyscallDesc("setreuid", unimplementedFunc), //32 bit
/* 127 */ SyscallDesc("setregid", unimplementedFunc), //32 bit
- /* 128 */ SyscallDesc("rename", unimplementedFunc),
+ /* 128 */ SyscallDesc("rename", renameFunc),
/* 129 */ SyscallDesc("truncate", unimplementedFunc),
/* 130 */ SyscallDesc("ftruncate", unimplementedFunc),
/* 131 */ SyscallDesc("flock", unimplementedFunc),
/* 125 */ SyscallDesc("recvfrom", unimplementedFunc),
/* 126 */ SyscallDesc("setreuid", unimplementedFunc),
/* 127 */ SyscallDesc("setregid", unimplementedFunc),
- /* 128 */ SyscallDesc("rename", unimplementedFunc),
+ /* 128 */ SyscallDesc("rename", renameFunc),
/* 129 */ SyscallDesc("truncate", unimplementedFunc),
/* 130 */ SyscallDesc("ftruncate", unimplementedFunc),
/* 131 */ SyscallDesc("flock", unimplementedFunc),
#endif
return;
case MISCREG_CWP:
- new_val = val > NWindows ? NWindows - 1 : val;
+ new_val = val >= NWindows ? NWindows - 1 : val;
+ if (val >= NWindows) {
+ new_val = NWindows - 1;
+ warn("Attempted to set the CWP to %d with NWindows = %d\n",
+ val, NWindows);
+ }
tc->changeRegFileContext(CONTEXT_CWP, new_val);
break;
case MISCREG_GL:
* Authors: Ali Saidi
*/
+#include "base/misc.hh"
+
#include <iostream>
#ifndef __BASE_BIGINT_HH__
b = x;
return *this;
}
+
+ operator uint64_t()
+ {
+ panic("Tried to cram a twin64_t into an integer!\n");
+ return a;
+ }
};
struct m5_twin32_t {
b = x;
return *this;
}
+
+ operator uint32_t()
+ {
+ panic("Tried to cram a twin32_t into an integer!\n");
+ return a;
+ }
};
#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+template
+Fault
+AtomicSimpleCPU::write(Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+AtomicSimpleCPU::write(Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
template
Fault
AtomicSimpleCPU::write(uint64_t data, Addr addr,
#ifndef DOXYGEN_SHOULD_SKIP_THIS
+template
+Fault
+TimingSimpleCPU::write(Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+TimingSimpleCPU::write(Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
template
Fault
TimingSimpleCPU::write(uint64_t data, Addr addr,
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-phase=0
-predType=tournament
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
-system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=gzip input.log 1
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-phase=0
-numThreads=1
-activity=0
-workload=system.cpu.workload
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 97621780 # Number of BTB hits
-global.BPredUnit.BTBLookups 104888901 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 203 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 4270829 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted
-global.BPredUnit.lookups 108029652 # Number of BP lookups
-global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target.
-host_inst_rate 64442 # Simulator instruction rate (inst/s)
-host_mem_usage 296420 # Number of bytes of host memory used
-host_seconds 8776.17 # Real time elapsed on the host
-host_tick_rate 192322 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 57063120 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 565552443 # Number of instructions simulated
-sim_seconds 0.001688 # Number of seconds simulated
-sim_ticks 1687849017 # Number of ticks simulated
-system.cpu.commit.COM:branches 62547159 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 17132854 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 701581491
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 480309675 6846.10%
- 1 104094392 1483.71%
- 2 40244499 573.63%
- 3 11990473 170.91%
- 4 15113210 215.42%
- 5 17360338 247.45%
- 6 10367558 147.77%
- 7 4968492 70.82%
- 8 17132854 244.20%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 601856963 # Number of instructions committed
-system.cpu.commit.COM:loads 115049510 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 154862033 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 4270194 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 331156834 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 565552443 # Number of Instructions Simulated
-system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
-system.cpu.cpi 2.984425 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.984425 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 114919015 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3573.284961 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3259.194046 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 114199728 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2570217420 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.006259 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 719287 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 495902 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 728055062 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 223385 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3753.412851 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3080.837357 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 38221364 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 4616536410 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.031177 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1229957 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 972712 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 792530006 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.006521 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 257245 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 329.539233 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 2285.588257 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 317.127712 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 3492 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 327032 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 1150751 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 747460499 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 154370336 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3686.944185 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 152421092 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7186753830 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.012627 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1949244 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 1468614 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1520585068 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003113 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 480630 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 154370336 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3686.944185 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 152421092 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7186753830 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.012627 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1949244 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 1468614 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1520585068 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003113 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 480630 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 476534 # number of replacements
-system.cpu.dcache.sampled_refs 480630 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4061.534340 # Cycle average of tags in use
-system.cpu.dcache.total_refs 152421092 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 22778000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 337990 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 113629190 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 667 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 4610173 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 1474333999 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 347767079 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 231043933 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 53597030 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 1980 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 9141290 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 108029652 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 167528188 # Number of cache lines fetched
-system.cpu.fetch.Cycles 410392582 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 7840605 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 1486495774 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 39151172 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.143052 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 167528188 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 99387598 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.968403 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 755178522
-system.cpu.fetch.rateDist.min_value 0
- 0 512314112 6784.01%
- 1 11453310 151.66%
- 2 16801464 222.48%
- 3 16318450 216.09%
- 4 18767749 248.52%
- 5 15201778 201.30%
- 6 32935567 436.13%
- 7 7297838 96.64%
- 8 124088254 1643.16%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 167528184 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5600.855285 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4703.251892 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 167526954 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 6889052 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1230 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 305 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 4350508 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 925 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 5880.941176 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 181110.220541 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 99976 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 167528184 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5600.855285 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency
-system.cpu.icache.demand_hits 167526954 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 6889052 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1230 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 305 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 4350508 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 925 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 167528184 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5600.855285 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 167526954 # number of overall hits
-system.cpu.icache.overall_miss_latency 6889052 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1230 # number of overall misses
-system.cpu.icache.overall_mshr_hits 305 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 4350508 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 925 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 47 # number of replacements
-system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 739.927243 # Cycle average of tags in use
-system.cpu.icache.total_refs 167526954 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 932670496 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 92484798 # Number of branches executed
-system.cpu.iew.EXEC:nop 154927960 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.987080 # Inst execution rate
-system.cpu.iew.EXEC:refs 253735466 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 51400640 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 486804101 # num instructions consuming a value
-system.cpu.iew.WB:count 671280122 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.809385 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 394011709 # num instructions producing a value
-system.cpu.iew.WB:rate 0.888903 # insts written-back per cycle
-system.cpu.iew.WB:sent 673021204 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 4738518 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 26824121 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 207074480 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 169524029 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 57063120 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 933012139 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 202334826 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 7294318 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 745421559 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 36474 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 1439 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 53597030 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 214253 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 5548 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 70837719 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 7377596 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 20150 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 1892 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 530187 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 4208331 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 0 0.00% # Type of FU issued
- IntAlu 496182294 65.92% # Type of FU issued
- IntMult 8208 0.00% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 33 0.00% # Type of FU issued
- FloatCmp 6 0.00% # Type of FU issued
- FloatCvt 5 0.00% # Type of FU issued
- FloatMult 5 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 204178453 27.13% # Type of FU issued
- MemWrite 52346873 6.95% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 3466320 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.004605 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 2723724 78.58% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 683243 19.71% # attempts to use FU when none available
- MemWrite 59353 1.71% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 755178522
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 450030250 5959.26%
- 1 91846319 1216.22%
- 2 83470092 1105.30%
- 3 53962116 714.56%
- 4 57175468 757.11%
- 5 10089384 133.60%
- 6 7448894 98.64%
- 7 1047122 13.87%
- 8 108877 1.44%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 0.996739 # Inst issue rate
-system.cpu.iq.iqInstsAdded 778084154 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 752715877 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 210836257 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 250496 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 119170992 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 481555 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 6806.870170 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2221.284395 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 455236 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 179150016 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.054654 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 26319 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 337990 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 337990 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 481555 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 6806.870170 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 455236 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 179150016 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.054654 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 26319 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 58461984 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.054654 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 26319 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 793226 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 26319 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 58461984 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.032114 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 26319 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 934 # number of replacements
-system.cpu.l2cache.sampled_refs 26319 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 24352.046438 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 793226 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 907 # number of writebacks
-system.cpu.numCycles 755178522 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 71954881 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 32102756 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 363513131 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 18414484 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 164520 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 1301215151 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 1374424300 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 698904999 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 224329578 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 53597030 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 41747264 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 235050110 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 36638 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 105666858 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed
-system.cpu.timesIdled 349047 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-simulate_stalls=false
-system=system
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-port=system.membus.port[0]
-
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=gzip input.log 1
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 970342 # Simulator instruction rate (inst/s)
-host_mem_usage 144620 # Number of bytes of host memory used
-host_seconds 620.25 # Real time elapsed on the host
-host_tick_rate 970342 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 601856965 # Number of instructions simulated
-sim_seconds 0.000602 # Number of seconds simulated
-sim_ticks 601856964 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 601856965 # number of cpu cycles simulated
-system.cpu.num_insts 601856965 # Number of instructions executed
-system.cpu.num_refs 154862034 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-system=system
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-port=system.membus.port[0]
-
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=gzip input.log 1
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 549029 # Simulator instruction rate (inst/s)
-host_mem_usage 300652 # Number of bytes of host memory used
-host_seconds 1096.22 # Real time elapsed on the host
-host_tick_rate 1916109 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 601856965 # Number of instructions simulated
-sim_seconds 0.002100 # Number of seconds simulated
-sim_ticks 2100480012 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 2845.396229 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1845.396229 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 572584774 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 371352774 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3026.723012 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2026.723012 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 769281001 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 515118001 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2946.597514 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 1341865775 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 886470775 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2946.597514 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 153509968 # number of overall hits
-system.cpu.dcache.overall_miss_latency 1341865775 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 455395 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 886470775 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 451299 # number of replacements
-system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4053.427393 # Cycle average of tags in use
-system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 33693000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 325723 # number of writebacks
-system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 4085.659119 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 3085.659119 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3248099 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 2453099 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 757051.787421 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 4085.659119 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency
-system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3248099 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
-system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 2453099 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 4085.659119 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 601856171 # number of overall hits
-system.cpu.icache.overall_miss_latency 3248099 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
-system.cpu.icache.overall_misses 795 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 2453099 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 24 # number of replacements
-system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 642.094524 # Cycle average of tags in use
-system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3251.348149 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1946.946471 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 84853684 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 50811409 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 325723 # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits 325723 # number of WriteReqNoAck|Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3251.348149 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 84853684 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 50811409 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3251.348149 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 755815 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 84853684 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 26098 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 50811409 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 903 # number of replacements
-system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 24085.007455 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 883 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 2100480012 # number of cpu cycles simulated
-system.cpu.num_insts 601856965 # Number of instructions executed
-system.cpu.num_refs 154862034 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-spec_init
-Loading Input Data
-Duplicating 262144 bytes
-Duplicating 524288 bytes
-Input data 1048576 bytes in length
-Compressing Input Data, level 1
-Compressed data 108074 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 3
-Compressed data 97831 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 5
-Compressed data 83382 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 7
-Compressed data 76606 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 73189 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache fuPool icache l2cache toL2Bus workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+phase=0
+numThreads=1
+activity=0
+workload=system.cpu.workload
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 97621780 # Number of BTB hits
+global.BPredUnit.BTBLookups 104888901 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 203 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 4270829 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted
+global.BPredUnit.lookups 108029652 # Number of BP lookups
+global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target.
+host_inst_rate 64442 # Simulator instruction rate (inst/s)
+host_mem_usage 296420 # Number of bytes of host memory used
+host_seconds 8776.17 # Real time elapsed on the host
+host_tick_rate 192322 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 57063120 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 565552443 # Number of instructions simulated
+sim_seconds 0.001688 # Number of seconds simulated
+sim_ticks 1687849017 # Number of ticks simulated
+system.cpu.commit.COM:branches 62547159 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 17132854 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 701581491
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 480309675 6846.10%
+ 1 104094392 1483.71%
+ 2 40244499 573.63%
+ 3 11990473 170.91%
+ 4 15113210 215.42%
+ 5 17360338 247.45%
+ 6 10367558 147.77%
+ 7 4968492 70.82%
+ 8 17132854 244.20%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 601856963 # Number of instructions committed
+system.cpu.commit.COM:loads 115049510 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 154862033 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 4270194 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 331156834 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 565552443 # Number of Instructions Simulated
+system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
+system.cpu.cpi 2.984425 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.984425 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 114919015 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3573.284961 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3259.194046 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 114199728 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2570217420 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.006259 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 719287 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 495902 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 728055062 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 223385 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3753.412851 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3080.837357 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 38221364 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4616536410 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.031177 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1229957 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 972712 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 792530006 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.006521 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 257245 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 329.539233 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 2285.588257 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 317.127712 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 3492 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 327032 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 1150751 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 747460499 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 154370336 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3686.944185 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 152421092 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7186753830 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.012627 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1949244 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1468614 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 1520585068 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003113 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 480630 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 154370336 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3686.944185 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 152421092 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7186753830 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.012627 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1949244 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1468614 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 1520585068 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003113 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 480630 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 476534 # number of replacements
+system.cpu.dcache.sampled_refs 480630 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4061.534340 # Cycle average of tags in use
+system.cpu.dcache.total_refs 152421092 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 22778000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 337990 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 113629190 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 667 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 4610173 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 1474333999 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 347767079 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 231043933 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 53597030 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1980 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 9141290 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 108029652 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 167528188 # Number of cache lines fetched
+system.cpu.fetch.Cycles 410392582 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 7840605 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 1486495774 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 39151172 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.143052 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 167528188 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 99387598 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.968403 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 755178522
+system.cpu.fetch.rateDist.min_value 0
+ 0 512314112 6784.01%
+ 1 11453310 151.66%
+ 2 16801464 222.48%
+ 3 16318450 216.09%
+ 4 18767749 248.52%
+ 5 15201778 201.30%
+ 6 32935567 436.13%
+ 7 7297838 96.64%
+ 8 124088254 1643.16%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 167528184 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5600.855285 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4703.251892 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 167526954 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 6889052 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1230 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 305 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 4350508 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 925 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 5880.941176 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 181110.220541 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 99976 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 167528184 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5600.855285 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency
+system.cpu.icache.demand_hits 167526954 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 6889052 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1230 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 305 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 4350508 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 925 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 167528184 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5600.855285 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 167526954 # number of overall hits
+system.cpu.icache.overall_miss_latency 6889052 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1230 # number of overall misses
+system.cpu.icache.overall_mshr_hits 305 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 4350508 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 925 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 47 # number of replacements
+system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 739.927243 # Cycle average of tags in use
+system.cpu.icache.total_refs 167526954 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 932670496 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 92484798 # Number of branches executed
+system.cpu.iew.EXEC:nop 154927960 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.987080 # Inst execution rate
+system.cpu.iew.EXEC:refs 253735466 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 51400640 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 486804101 # num instructions consuming a value
+system.cpu.iew.WB:count 671280122 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.809385 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 394011709 # num instructions producing a value
+system.cpu.iew.WB:rate 0.888903 # insts written-back per cycle
+system.cpu.iew.WB:sent 673021204 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 4738518 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 26824121 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 207074480 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 169524029 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 57063120 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 933012139 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 202334826 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 7294318 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 745421559 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 36474 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 1439 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 53597030 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 214253 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 5548 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 70837719 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 7377596 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 20150 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 1892 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 530187 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 4208331 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 496182294 65.92% # Type of FU issued
+ IntMult 8208 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 33 0.00% # Type of FU issued
+ FloatCmp 6 0.00% # Type of FU issued
+ FloatCvt 5 0.00% # Type of FU issued
+ FloatMult 5 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 204178453 27.13% # Type of FU issued
+ MemWrite 52346873 6.95% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 3466320 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.004605 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 2723724 78.58% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 683243 19.71% # attempts to use FU when none available
+ MemWrite 59353 1.71% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 755178522
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 450030250 5959.26%
+ 1 91846319 1216.22%
+ 2 83470092 1105.30%
+ 3 53962116 714.56%
+ 4 57175468 757.11%
+ 5 10089384 133.60%
+ 6 7448894 98.64%
+ 7 1047122 13.87%
+ 8 108877 1.44%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.996739 # Inst issue rate
+system.cpu.iq.iqInstsAdded 778084154 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 752715877 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 210836257 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 250496 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 119170992 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 481555 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 6806.870170 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2221.284395 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 455236 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 179150016 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.054654 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 26319 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 337990 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 337990 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 481555 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 6806.870170 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 455236 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 179150016 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.054654 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 26319 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 58461984 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.054654 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 26319 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 793226 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 26319 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 58461984 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.032114 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 26319 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 934 # number of replacements
+system.cpu.l2cache.sampled_refs 26319 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 24352.046438 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 793226 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 907 # number of writebacks
+system.cpu.numCycles 755178522 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 71954881 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 32102756 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 363513131 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 18414484 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 164520 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 1301215151 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 1374424300 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 698904999 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 224329578 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 53597030 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 41747264 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 235050110 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 36638 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 105666858 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed
+system.cpu.timesIdled 349047 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 970342 # Simulator instruction rate (inst/s)
+host_mem_usage 144620 # Number of bytes of host memory used
+host_seconds 620.25 # Real time elapsed on the host
+host_tick_rate 970342 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 601856965 # Number of instructions simulated
+sim_seconds 0.000602 # Number of seconds simulated
+sim_ticks 601856964 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 601856965 # number of cpu cycles simulated
+system.cpu.num_insts 601856965 # Number of instructions executed
+system.cpu.num_refs 154862034 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 549029 # Simulator instruction rate (inst/s)
+host_mem_usage 300652 # Number of bytes of host memory used
+host_seconds 1096.22 # Real time elapsed on the host
+host_tick_rate 1916109 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 601856965 # Number of instructions simulated
+sim_seconds 0.002100 # Number of seconds simulated
+sim_ticks 2100480012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 2845.396229 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1845.396229 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 572584774 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 371352774 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3026.723012 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2026.723012 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 769281001 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 515118001 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 2946.597514 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 1341865775 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 886470775 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 2946.597514 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 153509968 # number of overall hits
+system.cpu.dcache.overall_miss_latency 1341865775 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 455395 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 886470775 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 451299 # number of replacements
+system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4053.427393 # Cycle average of tags in use
+system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 33693000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 325723 # number of writebacks
+system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4085.659119 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3085.659119 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 3248099 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 2453099 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 757051.787421 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4085.659119 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency
+system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 3248099 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
+system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 2453099 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4085.659119 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 601856171 # number of overall hits
+system.cpu.icache.overall_miss_latency 3248099 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
+system.cpu.icache.overall_misses 795 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 2453099 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 24 # number of replacements
+system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 642.094524 # Cycle average of tags in use
+system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3251.348149 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1946.946471 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 84853684 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 50811409 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 325723 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 325723 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3251.348149 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 84853684 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 50811409 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3251.348149 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 755815 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 84853684 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 26098 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 50811409 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 903 # number of replacements
+system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 24085.007455 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 883 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 2100480012 # number of cpu cycles simulated
+system.cpu.num_insts 601856965 # Number of instructions executed
+system.cpu.num_refs 154862034 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
m5.AddToPath('../configs/common')
from cpu2000 import gzip_log
-workload = gzip_log('alpha', 'tru64', 'smred')
+workload = gzip_log(isa, opsys, 'smred')
root.system.cpu.workload = workload.makeLiveProcess()
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
m5.AddToPath('../configs/common')
from cpu2000 import mcf
-workload = mcf('alpha', 'tru64', 'lgred')
+workload = mcf(isa, opsys, 'lgred')
root.system.cpu.workload = workload.makeLiveProcess()
+++ /dev/null
-I removed the reference outputs for this program because it's taking
-way too long... over an hour for simple-atomic and over 19 hrs for
-o3-timing. We need to find a shorter input if we want to keep this
-in the regressions.
-
-Steve
--- /dev/null
+I removed the reference outputs for this program because it's taking
+way too long... over an hour for simple-atomic and over 19 hrs for
+o3-timing. We need to find a shorter input if we want to keep this
+in the regressions.
+
+Steve
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
m5.AddToPath('../configs/common')
from cpu2000 import parser
-workload = parser('alpha', 'tru64', 'lgred')
+workload = parser(isa, opsys, 'lgred')
root.system.cpu.workload = workload.makeLiveProcess()
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-phase=0
-predType=tournament
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
-system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/o3-timing
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/o3-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-phase=0
-numThreads=1
-activity=0
-workload=system.cpu.workload
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 38046005 # Number of BTB hits
-global.BPredUnit.BTBLookups 46765160 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1072 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 5897447 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 36345249 # Number of conditional branches predicted
-global.BPredUnit.lookups 64275681 # Number of BP lookups
-global.BPredUnit.usedRAS 12928446 # Number of times the RAS was used to get a target.
-host_inst_rate 88491 # Simulator instruction rate (inst/s)
-host_mem_usage 183984 # Number of bytes of host memory used
-host_seconds 4244.22 # Real time elapsed on the host
-host_tick_rate 69460 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 64217134 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 49870920 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 126084683 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 92646936 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 375574675 # Number of instructions simulated
-sim_seconds 0.000295 # Number of seconds simulated
-sim_ticks 294803028 # Number of ticks simulated
-system.cpu.commit.COM:branches 44587523 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 16167573 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 260352657
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 139362663 5352.84%
- 1 37755491 1450.17%
- 2 23927219 919.03%
- 3 17243764 662.32%
- 4 9550787 366.84%
- 5 7718539 296.46%
- 6 5199548 199.71%
- 7 3427073 131.63%
- 8 16167573 620.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 398664447 # Number of instructions committed
-system.cpu.commit.COM:loads 100651988 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 174183388 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 5893264 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 398664447 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 98024957 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 375574675 # Number of Instructions Simulated
-system.cpu.committedInsts_total 375574675 # Number of Instructions Simulated
-system.cpu.cpi 0.784939 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.784939 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 94465294 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5573.350269 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5155.812183 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 94463621 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 9324215 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1673 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 688 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 5078475 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 5442.694460 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5169.706416 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73508218 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 68082665 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000170 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 12509 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 9314 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 16517212 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 2708.631579 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 3690.984252 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40184.650478 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 19 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 2032 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 51464 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 7500080 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 167986021 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 5458.107460 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 167971839 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 77406880 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 14182 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 10002 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 21595687 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4180 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 167986021 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 5458.107460 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 167971839 # number of overall hits
-system.cpu.dcache.overall_miss_latency 77406880 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 14182 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 10002 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 21595687 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4180 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 784 # number of replacements
-system.cpu.dcache.sampled_refs 4180 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3190.140908 # Cycle average of tags in use
-system.cpu.dcache.total_refs 167971839 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 637 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 19324711 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 4274 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 11555430 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 538406721 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 137426232 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 102617017 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 16124012 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 12594 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 984698 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 64275681 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 66044385 # Number of cache lines fetched
-system.cpu.fetch.Cycles 172472243 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1233740 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 552850318 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 6527825 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.232481 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 66044385 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 50974451 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.999627 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 276476670
-system.cpu.fetch.rateDist.min_value 0
- 0 170048750 6150.56%
- 1 11707777 423.46%
- 2 11563595 418.25%
- 3 7250668 262.25%
- 4 16393688 592.95%
- 5 9178756 331.99%
- 6 6871715 248.55%
- 7 4129243 149.35%
- 8 39332478 1422.63%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 66044384 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 4697.455355 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 3736.572860 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 66039333 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 23726847 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 5051 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 1160 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 14539005 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000059 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 3891 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 5023.260870 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 16972.329221 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 69 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 346605 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 66044384 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 4697.455355 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency
-system.cpu.icache.demand_hits 66039333 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 23726847 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
-system.cpu.icache.demand_misses 5051 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 1160 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 14539005 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000059 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 3891 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 66044384 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 4697.455355 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 66039333 # number of overall hits
-system.cpu.icache.overall_miss_latency 23726847 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
-system.cpu.icache.overall_misses 5051 # number of overall misses
-system.cpu.icache.overall_mshr_hits 1160 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 14539005 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000059 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 3891 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1971 # number of replacements
-system.cpu.icache.sampled_refs 3891 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1776.887115 # Cycle average of tags in use
-system.cpu.icache.total_refs 66039333 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 18326359 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 51280930 # Number of branches executed
-system.cpu.iew.EXEC:nop 27455299 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.521589 # Inst execution rate
-system.cpu.iew.EXEC:refs 191354897 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 79285920 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 293982680 # num instructions consuming a value
-system.cpu.iew.WB:count 415403944 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.694108 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 204055700 # num instructions producing a value
-system.cpu.iew.WB:rate 1.502492 # insts written-back per cycle
-system.cpu.iew.WB:sent 416259284 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 6316593 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 2856011 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 126084683 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 240 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 7411275 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 92646936 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 496689311 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 112068977 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 8996952 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 420683841 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 114816 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 1986 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 16124012 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 416926 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 183286 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 727659 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 9888553 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 47660 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 81366 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 183286 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 25432695 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 19115536 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 81366 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 996952 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 5319641 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.273985 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.273985 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 429680793 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 33581 0.01% # Type of FU issued
- IntAlu 167723328 39.03% # Type of FU issued
- IntMult 2137299 0.50% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 34928239 8.13% # Type of FU issued
- FloatCmp 8071357 1.88% # Type of FU issued
- FloatCvt 3141242 0.73% # Type of FU issued
- FloatMult 16626981 3.87% # Type of FU issued
- FloatDiv 1577676 0.37% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 114426564 26.63% # Type of FU issued
- MemWrite 81014526 18.85% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 9055324 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.021075 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 66610 0.74% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 110487 1.22% # attempts to use FU when none available
- FloatCmp 35273 0.39% # attempts to use FU when none available
- FloatCvt 2828 0.03% # attempts to use FU when none available
- FloatMult 2149754 23.74% # attempts to use FU when none available
- FloatDiv 664669 7.34% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 4545406 50.20% # attempts to use FU when none available
- MemWrite 1480297 16.35% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 276476670
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 105552217 3817.76%
- 1 55104063 1993.08%
- 2 43517427 1574.00%
- 3 31483356 1138.73%
- 4 21726208 785.82%
- 5 11633875 420.79%
- 6 4624667 167.27%
- 7 2409257 87.14%
- 8 425600 15.39%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.554130 # Inst issue rate
-system.cpu.iq.iqInstsAdded 469233772 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 429680793 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 240 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 93305351 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 1513608 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 71392848 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 4399.297838 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2193.473956 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 717 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 32348037 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.911152 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 7353 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 16128614 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911152 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 7353 # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 637 # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits 637 # number of WriteReqNoAck|Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.184143 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 4399.297838 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 717 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 32348037 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.911152 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7353 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 16128614 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.911152 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7353 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 4399.297838 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1354 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 32348037 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.844493 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7353 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 16128614 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.844493 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7353 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 7353 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 6415.706550 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1354 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 276476670 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 8743693 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 259532206 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 653030 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 142074266 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 8196045 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 687565953 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 524563034 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 338654872 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 98656303 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 16124012 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 9950983 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 79122666 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 927413 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 40317 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 23109451 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 249 # count of temporary serializing insts renamed
-system.cpu.timesIdled 6216 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7002
-warn: Entering event queue @ 0. Starting simulation...
-getting pixel output filename pixels_out.cook
-opening control file chair.control.cook
-opening camera file chair.camera
-opening surfaces file chair.surfaces
-reading data
-processing 8parts
-Grid measure is 6 by 3.0001 by 6
-cell dimension is 0.863065
-Creating grid for list of length 21
-Grid size = 7 by 4 by 7
-Total occupancy = 236
-reading control stream
-reading camera stream
-Writing to chair.cook.ppm
-calculating 15 by 15 image with 196 samples
-col 0. . .
-col 1. . .
-col 2. . .
-col 3. . .
-col 4. . .
-col 5. . .
-col 6. . .
-col 7. . .
-col 8. . .
-col 9. . .
-col 10. . .
-col 11. . .
-col 12. . .
-col 13. . .
-col 14. . .
-Writing to chair.cook.ppm
-0 8 14
-1 8 14
-2 8 14
-3 8 14
-4 8 14
-5 8 14
-6 8 14
-7 8 14
-8 8 14
-9 8 14
-10 8 14
-11 8 14
-12 8 14
-13 8 14
-14 8 14
+++ /dev/null
-Eon, Version 1.1
-OO-style eon Time= 0.000000
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-simulate_stalls=false
-system=system
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-port=system.membus.port[0]
-
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 841426 # Simulator instruction rate (inst/s)
-host_mem_usage 147172 # Number of bytes of host memory used
-host_seconds 473.80 # Real time elapsed on the host
-host_tick_rate 841425 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 398664450 # Number of instructions simulated
-sim_seconds 0.000399 # Number of seconds simulated
-sim_ticks 398664449 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 398664450 # number of cpu cycles simulated
-system.cpu.num_insts 398664450 # Number of instructions executed
-system.cpu.num_refs 174183390 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-warn: Entering event queue @ 0. Starting simulation...
-getting pixel output filename pixels_out.cook
-opening control file chair.control.cook
-opening camera file chair.camera
-opening surfaces file chair.surfaces
-reading data
-processing 8parts
-Grid measure is 6 by 3.0001 by 6
-cell dimension is 0.863065
-Creating grid for list of length 21
-Grid size = 7 by 4 by 7
-Total occupancy = 236
-reading control stream
-reading camera stream
-Writing to chair.cook.ppm
-calculating 15 by 15 image with 196 samples
-col 0. . .
-col 1. . .
-col 2. . .
-col 3. . .
-col 4. . .
-col 5. . .
-col 6. . .
-col 7. . .
-col 8. . .
-col 9. . .
-col 10. . .
-col 11. . .
-col 12. . .
-col 13. . .
-col 14. . .
-Writing to chair.cook.ppm
-0 8 14
-1 8 14
-2 8 14
-3 8 14
-4 8 14
-5 8 14
-6 8 14
-7 8 14
-8 8 14
-9 8 14
-10 8 14
-11 8 14
-12 8 14
-13 8 14
-14 8 14
+++ /dev/null
-Eon, Version 1.1
-OO-style eon Time= 0.000000
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-system=system
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing
-egid=100
-env=
-euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 689508 # Simulator instruction rate (inst/s)
-host_mem_usage 185012 # Number of bytes of host memory used
-host_seconds 578.19 # Real time elapsed on the host
-host_tick_rate 1033135 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 398664450 # Number of instructions simulated
-sim_seconds 0.000597 # Number of seconds simulated
-sim_ticks 597346012 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 94753532 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3758780 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 168271057 # number of overall hits
-system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 4152 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 764 # number of replacements
-system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use
-system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 625 # number of writebacks
-system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency
-system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
-system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 398660777 # number of overall hits
-system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
-system.cpu.icache.overall_misses 3674 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1770 # number of replacements
-system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use
-system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1276 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7175 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 597346012 # number of cpu cycles simulated
-system.cpu.num_insts 398664450 # Number of instructions executed
-system.cpu.num_refs 174183390 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
-getting pixel output filename pixels_out.cook
-opening control file chair.control.cook
-opening camera file chair.camera
-opening surfaces file chair.surfaces
-reading data
-processing 8parts
-Grid measure is 6 by 3.0001 by 6
-cell dimension is 0.863065
-Creating grid for list of length 21
-Grid size = 7 by 4 by 7
-Total occupancy = 236
-reading control stream
-reading camera stream
-Writing to chair.cook.ppm
-calculating 15 by 15 image with 196 samples
-col 0. . .
-col 1. . .
-col 2. . .
-col 3. . .
-col 4. . .
-col 5. . .
-col 6. . .
-col 7. . .
-col 8. . .
-col 9. . .
-col 10. . .
-col 11. . .
-col 12. . .
-col 13. . .
-col 14. . .
-Writing to chair.cook.ppm
-0 8 14
-1 8 14
-2 8 14
-3 8 14
-4 8 14
-5 8 14
-6 8 14
-7 8 14
-8 8 14
-9 8 14
-10 8 14
-11 8 14
-12 8 14
-13 8 14
-14 8 14
+++ /dev/null
-Eon, Version 1.1
-OO-style eon Time= 0.000000
--- /dev/null
+[root]
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+
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+
--- /dev/null
+[root]
+type=Root
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+
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+[system]
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+
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+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 38046005 # Number of BTB hits
+global.BPredUnit.BTBLookups 46765160 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1072 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 5897447 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 36345249 # Number of conditional branches predicted
+global.BPredUnit.lookups 64275681 # Number of BP lookups
+global.BPredUnit.usedRAS 12928446 # Number of times the RAS was used to get a target.
+host_inst_rate 88491 # Simulator instruction rate (inst/s)
+host_mem_usage 183984 # Number of bytes of host memory used
+host_seconds 4244.22 # Real time elapsed on the host
+host_tick_rate 69460 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 64217134 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 49870920 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 126084683 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 92646936 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 375574675 # Number of instructions simulated
+sim_seconds 0.000295 # Number of seconds simulated
+sim_ticks 294803028 # Number of ticks simulated
+system.cpu.commit.COM:branches 44587523 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 16167573 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 260352657
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 139362663 5352.84%
+ 1 37755491 1450.17%
+ 2 23927219 919.03%
+ 3 17243764 662.32%
+ 4 9550787 366.84%
+ 5 7718539 296.46%
+ 6 5199548 199.71%
+ 7 3427073 131.63%
+ 8 16167573 620.99%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 398664447 # Number of instructions committed
+system.cpu.commit.COM:loads 100651988 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 174183388 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 5893264 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 398664447 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 98024957 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 375574675 # Number of Instructions Simulated
+system.cpu.committedInsts_total 375574675 # Number of Instructions Simulated
+system.cpu.cpi 0.784939 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.784939 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 94465294 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5573.350269 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5155.812183 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 94463621 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 9324215 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1673 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 688 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 5078475 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 5442.694460 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5169.706416 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 73508218 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 68082665 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000170 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 12509 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 9314 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 16517212 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 2708.631579 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 3690.984252 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 40184.650478 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 19 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 2032 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 51464 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 7500080 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 167986021 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 5458.107460 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 167971839 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 77406880 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 14182 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 10002 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 21595687 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 4180 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 167986021 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 5458.107460 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 167971839 # number of overall hits
+system.cpu.dcache.overall_miss_latency 77406880 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 14182 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 10002 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 21595687 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 4180 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 784 # number of replacements
+system.cpu.dcache.sampled_refs 4180 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 3190.140908 # Cycle average of tags in use
+system.cpu.dcache.total_refs 167971839 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 637 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 19324711 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 4274 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 11555430 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 538406721 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 137426232 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 102617017 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 16124012 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 12594 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 984698 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 64275681 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 66044385 # Number of cache lines fetched
+system.cpu.fetch.Cycles 172472243 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1233740 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 552850318 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 6527825 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.232481 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 66044385 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 50974451 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.999627 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 276476670
+system.cpu.fetch.rateDist.min_value 0
+ 0 170048750 6150.56%
+ 1 11707777 423.46%
+ 2 11563595 418.25%
+ 3 7250668 262.25%
+ 4 16393688 592.95%
+ 5 9178756 331.99%
+ 6 6871715 248.55%
+ 7 4129243 149.35%
+ 8 39332478 1422.63%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 66044384 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4697.455355 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3736.572860 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 66039333 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 23726847 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 5051 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 1160 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 14539005 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000059 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 3891 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 5023.260870 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 16972.329221 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 69 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 346605 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 66044384 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4697.455355 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency
+system.cpu.icache.demand_hits 66039333 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 23726847 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
+system.cpu.icache.demand_misses 5051 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 1160 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 14539005 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000059 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 3891 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 66044384 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4697.455355 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 66039333 # number of overall hits
+system.cpu.icache.overall_miss_latency 23726847 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
+system.cpu.icache.overall_misses 5051 # number of overall misses
+system.cpu.icache.overall_mshr_hits 1160 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 14539005 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000059 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 3891 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1971 # number of replacements
+system.cpu.icache.sampled_refs 3891 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1776.887115 # Cycle average of tags in use
+system.cpu.icache.total_refs 66039333 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 18326359 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 51280930 # Number of branches executed
+system.cpu.iew.EXEC:nop 27455299 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.521589 # Inst execution rate
+system.cpu.iew.EXEC:refs 191354897 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 79285920 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 293982680 # num instructions consuming a value
+system.cpu.iew.WB:count 415403944 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.694108 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 204055700 # num instructions producing a value
+system.cpu.iew.WB:rate 1.502492 # insts written-back per cycle
+system.cpu.iew.WB:sent 416259284 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 6316593 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2856011 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 126084683 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 240 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 7411275 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 92646936 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 496689311 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 112068977 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 8996952 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 420683841 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 114816 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 1986 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 16124012 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 416926 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 183286 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 727659 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 9888553 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 47660 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 81366 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 183286 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 25432695 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 19115536 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 81366 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 996952 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 5319641 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.273985 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.273985 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 429680793 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 33581 0.01% # Type of FU issued
+ IntAlu 167723328 39.03% # Type of FU issued
+ IntMult 2137299 0.50% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 34928239 8.13% # Type of FU issued
+ FloatCmp 8071357 1.88% # Type of FU issued
+ FloatCvt 3141242 0.73% # Type of FU issued
+ FloatMult 16626981 3.87% # Type of FU issued
+ FloatDiv 1577676 0.37% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 114426564 26.63% # Type of FU issued
+ MemWrite 81014526 18.85% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 9055324 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.021075 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 66610 0.74% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 110487 1.22% # attempts to use FU when none available
+ FloatCmp 35273 0.39% # attempts to use FU when none available
+ FloatCvt 2828 0.03% # attempts to use FU when none available
+ FloatMult 2149754 23.74% # attempts to use FU when none available
+ FloatDiv 664669 7.34% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 4545406 50.20% # attempts to use FU when none available
+ MemWrite 1480297 16.35% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 276476670
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 105552217 3817.76%
+ 1 55104063 1993.08%
+ 2 43517427 1574.00%
+ 3 31483356 1138.73%
+ 4 21726208 785.82%
+ 5 11633875 420.79%
+ 6 4624667 167.27%
+ 7 2409257 87.14%
+ 8 425600 15.39%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.554130 # Inst issue rate
+system.cpu.iq.iqInstsAdded 469233772 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 429680793 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 240 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 93305351 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 1513608 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 71392848 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4399.297838 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2193.473956 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 717 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 32348037 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.911152 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 7353 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 16128614 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911152 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 7353 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 637 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 637 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.184143 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4399.297838 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 717 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 32348037 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.911152 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7353 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 16128614 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.911152 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7353 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4399.297838 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 1354 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 32348037 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.844493 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7353 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 16128614 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.844493 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7353 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 7353 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 6415.706550 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1354 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 276476670 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 8743693 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 259532206 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 653030 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 142074266 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 8196045 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 687565953 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 524563034 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 338654872 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 98656303 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 16124012 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 9950983 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 79122666 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 927413 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 40317 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 23109451 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 249 # count of temporary serializing insts renamed
+system.cpu.timesIdled 6216 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7002
+warn: Entering event queue @ 0. Starting simulation...
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
--- /dev/null
+Eon, Version 1.1
+OO-style eon Time= 0.000000
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 841426 # Simulator instruction rate (inst/s)
+host_mem_usage 147172 # Number of bytes of host memory used
+host_seconds 473.80 # Real time elapsed on the host
+host_tick_rate 841425 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 398664450 # Number of instructions simulated
+sim_seconds 0.000399 # Number of seconds simulated
+sim_ticks 398664449 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 398664450 # number of cpu cycles simulated
+system.cpu.num_insts 398664450 # Number of instructions executed
+system.cpu.num_refs 174183390 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
--- /dev/null
+Eon, Version 1.1
+OO-style eon Time= 0.000000
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 689508 # Simulator instruction rate (inst/s)
+host_mem_usage 185012 # Number of bytes of host memory used
+host_seconds 578.19 # Real time elapsed on the host
+host_tick_rate 1033135 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 398664450 # Number of instructions simulated
+sim_seconds 0.000597 # Number of seconds simulated
+sim_ticks 597346012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 94753532 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3758780 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 168271057 # number of overall hits
+system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 4152 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 764 # number of replacements
+system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use
+system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 625 # number of writebacks
+system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency
+system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
+system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 398660777 # number of overall hits
+system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
+system.cpu.icache.overall_misses 3674 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1770 # number of replacements
+system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use
+system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 1276 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7175 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 597346012 # number of cpu cycles simulated
+system.cpu.num_insts 398664450 # Number of instructions executed
+system.cpu.num_refs 174183390 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
--- /dev/null
+Eon, Version 1.1
+OO-style eon Time= 0.000000
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
m5.AddToPath('../configs/common')
from cpu2000 import eon_cook
-workload = eon_cook('alpha', 'tru64', 'mdred')
+workload = eon_cook(isa, opsys, 'mdred')
root.system.cpu.workload = workload.makeLiveProcess()
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-simulate_stalls=false
-system=system
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
-egid=100
-env=
-euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1149393 # Simulator instruction rate (inst/s)
-host_mem_usage 177516 # Number of bytes of host memory used
-host_seconds 1747.87 # Real time elapsed on the host
-host_tick_rate 1149393 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2008987607 # Number of instructions simulated
-sim_seconds 0.002009 # Number of seconds simulated
-sim_ticks 2008987606 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 2008987607 # number of cpu cycles simulated
-system.cpu.num_insts 2008987607 # Number of instructions executed
-system.cpu.num_refs 722390435 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
-warn: ignoring syscall sigprocmask(1, 0, ...)
+++ /dev/null
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-0: 2206428413
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-system=system
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
-egid=100
-env=
-euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 752631 # Simulator instruction rate (inst/s)
-host_mem_usage 230876 # Number of bytes of host memory used
-host_seconds 2669.29 # Real time elapsed on the host
-host_tick_rate 2836913 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2008987607 # Number of instructions simulated
-sim_seconds 0.007573 # Number of seconds simulated
-sim_ticks 7572532003 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3107.171986 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171986 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4530853333 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3072661333 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3884.267929 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.267929 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 279480846 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 207528846 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3143.713388 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 4810334179 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3280190179 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3143.713388 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 720334778 # number of overall hits
-system.cpu.dcache.overall_miss_latency 4810334179 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1530144 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3280190179 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 1526048 # number of replacements
-system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4087.479154 # Cycle average of tags in use
-system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 35165000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 74589 # number of writebacks
-system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3103.627312 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.627312 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 32886035 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 22290035 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3103.627312 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency
-system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 32886035 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
-system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 22290035 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3103.627312 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 2008977012 # number of overall hits
-system.cpu.icache.overall_miss_latency 32886035 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
-system.cpu.icache.overall_misses 10596 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 22290035 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 9046 # number of replacements
-system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1471.254279 # Cycle average of tags in use
-system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2153.828221 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.659139 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 3245521901 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1675116913 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 73515 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.014399 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 1074 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.014399 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 1074 # number of Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.071269 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2153.828221 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 3245521901 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 1675116913 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2152.294196 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 107393 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 3245521901 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 1507936 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 1675116913 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 1474094 # number of replacements
-system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 32444.706916 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 164189000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 66804 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 7572532003 # number of cpu cycles simulated
-system.cpu.num_insts 2008987607 # Number of instructions executed
-system.cpu.num_refs 722390435 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
-warn: ignoring syscall sigprocmask(1, 0, ...)
+++ /dev/null
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--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
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+
+[serialize]
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+[stats]
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+
+[system]
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+children=cpu membus physmem
+mem_mode=atomic
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+
+[system.cpu]
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+[system.cpu.workload]
+type=LiveProcess
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+[system.membus]
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+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
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+[system.physmem]
+type=PhysicalMemory
+file=
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+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
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+[system.physmem]
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+[system]
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+input=cin
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+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1149393 # Simulator instruction rate (inst/s)
+host_mem_usage 177516 # Number of bytes of host memory used
+host_seconds 1747.87 # Real time elapsed on the host
+host_tick_rate 1149393 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2008987607 # Number of instructions simulated
+sim_seconds 0.002009 # Number of seconds simulated
+sim_ticks 2008987606 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 2008987607 # number of cpu cycles simulated
+system.cpu.num_insts 2008987607 # Number of instructions executed
+system.cpu.num_refs 722390435 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
+warn: ignoring syscall sigprocmask(1, 0, ...)
--- /dev/null
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--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 752631 # Simulator instruction rate (inst/s)
+host_mem_usage 230876 # Number of bytes of host memory used
+host_seconds 2669.29 # Real time elapsed on the host
+host_tick_rate 2836913 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2008987607 # Number of instructions simulated
+sim_seconds 0.007573 # Number of seconds simulated
+sim_ticks 7572532003 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3107.171986 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171986 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4530853333 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3072661333 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3884.267929 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.267929 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 279480846 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 207528846 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3143.713388 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 4810334179 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 3280190179 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3143.713388 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 720334778 # number of overall hits
+system.cpu.dcache.overall_miss_latency 4810334179 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1530144 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 3280190179 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 1526048 # number of replacements
+system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4087.479154 # Cycle average of tags in use
+system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 35165000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 74589 # number of writebacks
+system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3103.627312 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.627312 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 32886035 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 22290035 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3103.627312 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency
+system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits
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+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.icache.overall_avg_miss_latency 3103.627312 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency
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+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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+system.cpu.icache.tagsinuse 1471.254279 # Cycle average of tags in use
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+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2153.828221 # average ReadReq miss latency
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+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.l2cache.warmup_cycle 164189000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 66804 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 7572532003 # number of cpu cycles simulated
+system.cpu.num_insts 2008987607 # Number of instructions executed
+system.cpu.num_refs 722390435 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
+warn: ignoring syscall sigprocmask(1, 0, ...)
--- /dev/null
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-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
m5.AddToPath('../configs/common')
from cpu2000 import perlbmk_makerand
-workload = perlbmk_makerand('alpha', 'tru64', 'lgred')
+workload = perlbmk_makerand(isa, opsys, 'lgred')
root.system.cpu.workload = workload.makeLiveProcess()
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-phase=0
-predType=tournament
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
-system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-phase=0
-numThreads=1
-activity=0
-workload=system.cpu.workload
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 13202034 # Number of BTB hits
-global.BPredUnit.BTBLookups 22107115 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 30370 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 454360 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 16498204 # Number of conditional branches predicted
-global.BPredUnit.lookups 27047110 # Number of BP lookups
-global.BPredUnit.usedRAS 4878193 # Number of times the RAS was used to get a target.
-host_inst_rate 69520 # Simulator instruction rate (inst/s)
-host_mem_usage 239908 # Number of bytes of host memory used
-host_seconds 1144.87 # Real time elapsed on the host
-host_tick_rate 987535 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 14725847 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 11490673 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 28863760 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 16312214 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 79591756 # Number of instructions simulated
-sim_seconds 0.001131 # Number of seconds simulated
-sim_ticks 1130602014 # Number of ticks simulated
-system.cpu.commit.COM:branches 13754477 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3893678 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 89505192
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 62882698 7025.59%
- 1 8753972 978.04%
- 2 5175203 578.20%
- 3 3243621 362.39%
- 4 2169519 242.39%
- 5 1432847 160.09%
- 6 1161882 129.81%
- 7 791772 88.46%
- 8 3893678 435.02%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 88340672 # Number of instructions committed
-system.cpu.commit.COM:loads 20379399 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 35224018 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 359967 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 21665941 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 79591756 # Number of Instructions Simulated
-system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 14.205014 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 14.205014 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 19540231 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 4453.766964 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3237.815878 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 19382637 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 701886951 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.008065 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 157594 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 95950 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 199591922 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.003155 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 61644 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4830.124895 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3999.409028 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 13942631 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3239786953 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.045899 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 670746 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 527274 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 573803212 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 143472 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 3332.672727 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 3759.399862 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 162.470348 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 125901 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 366594 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 473312202 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 34153608 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4758.521747 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 33325268 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 3941673904 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.024253 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 828340 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 623224 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 773395134 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006006 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 205116 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 34153608 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4758.521747 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 33325268 # number of overall hits
-system.cpu.dcache.overall_miss_latency 3941673904 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.024253 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 828340 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 623224 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 773395134 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006006 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 205116 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 201020 # number of replacements
-system.cpu.dcache.sampled_refs 205116 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4057.039034 # Cycle average of tags in use
-system.cpu.dcache.total_refs 33325268 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 27784000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147771 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 11948269 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 95198 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3558048 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 131593428 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 51674084 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 25481309 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 4702945 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 281359 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 401531 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 27047110 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 22733117 # Number of cache lines fetched
-system.cpu.fetch.Cycles 51481541 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 159026 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 148267180 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 3966980 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.287100 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 22733117 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 18080227 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.573826 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 94208138
-system.cpu.fetch.rateDist.min_value 0
- 0 65459635 6948.41%
- 1 1687117 179.08%
- 2 1748812 185.63%
- 3 1938924 205.81%
- 4 6981531 741.08%
- 5 6100701 647.58%
- 6 758078 80.47%
- 7 1979150 210.08%
- 8 7554190 801.86%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 22733116 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3345.551905 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2359.548288 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 22631700 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 339292492 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.004461 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 101416 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 13878 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 206550138 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.003851 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 87538 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 3731.567010 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 258.538675 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 97 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 361962 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 22733116 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3345.551905 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency
-system.cpu.icache.demand_hits 22631700 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 339292492 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.004461 # miss rate for demand accesses
-system.cpu.icache.demand_misses 101416 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 13878 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 206550138 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.003851 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 87538 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 22733116 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3345.551905 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 22631700 # number of overall hits
-system.cpu.icache.overall_miss_latency 339292492 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.004461 # miss rate for overall accesses
-system.cpu.icache.overall_misses 101416 # number of overall misses
-system.cpu.icache.overall_mshr_hits 13878 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 206550138 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.003851 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 87538 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 85490 # number of replacements
-system.cpu.icache.sampled_refs 87537 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1835.330854 # Cycle average of tags in use
-system.cpu.icache.total_refs 22631700 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1036393877 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 14379719 # Number of branches executed
-system.cpu.iew.EXEC:nop 9265977 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.989418 # Inst execution rate
-system.cpu.iew.EXEC:refs 43156162 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 15338261 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 46157981 # num instructions consuming a value
-system.cpu.iew.WB:count 86105601 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.741496 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 34225955 # num instructions producing a value
-system.cpu.iew.WB:rate 0.913993 # insts written-back per cycle
-system.cpu.iew.WB:sent 86171133 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 389534 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 3213991 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 28863760 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 4784 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1402526 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 16312214 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 110003367 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 27817901 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 453087 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 93211232 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 28742 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 12962 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 4702945 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 194395 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1528 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 6922047 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 1365052 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5008 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 3825 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1528 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 8484361 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1467595 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 3825 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 102872 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 286662 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.070398 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.070398 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 93664319 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 0 0.00% # Type of FU issued
- IntAlu 49995908 53.38% # Type of FU issued
- IntMult 43196 0.05% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 123595 0.13% # Type of FU issued
- FloatCmp 86 0.00% # Type of FU issued
- FloatCvt 122386 0.13% # Type of FU issued
- FloatMult 51 0.00% # Type of FU issued
- FloatDiv 37853 0.04% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 27919833 29.81% # Type of FU issued
- MemWrite 15421411 16.46% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 1229792 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013130 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 83895 6.82% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 589327 47.92% # attempts to use FU when none available
- MemWrite 556570 45.26% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 94208138
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 54322746 5766.25%
- 1 13333515 1415.33%
- 2 10626230 1127.95%
- 3 8813553 935.54%
- 4 4440243 471.32%
- 5 1597603 169.58%
- 6 685526 72.77%
- 7 334234 35.48%
- 8 54488 5.78%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 0.994227 # Inst issue rate
-system.cpu.iq.iqInstsAdded 100732606 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 93664319 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 4784 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 20911338 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 73995 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 16334966 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 292646 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3929.598028 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2043.469607 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 122985 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 666699531 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.579748 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 169661 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 346697097 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579748 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 169661 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147771 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147307 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.593139 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 292646 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3929.598028 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 122985 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 666699531 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.579748 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 169661 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 346697097 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.579748 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 169661 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 440417 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3918.880417 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 270292 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 666699531 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.386282 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 170125 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 346697097 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.385228 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 169661 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 136892 # number of replacements
-system.cpu.l2cache.sampled_refs 169660 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 30349.297230 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 270292 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 625483000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 115938 # number of writebacks
-system.cpu.numCycles 94208138 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 7563765 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 87866 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 52361095 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 3315491 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 3509 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 154857350 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 130101763 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 82913656 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 25182526 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 4702945 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 3542613 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 30366775 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 855194 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 4773 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 6398047 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 4771 # count of temporary serializing insts renamed
-system.cpu.timesIdled 275758 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := True
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 8
- sizeof(longaddr ) = 8
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 8
- sizeof(char * ) = 8
- ALLOC CORE_1 :: 16
- BHOOLE NATH
-
- OPEN File ./input/lendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 40054800
-
- OPEN File ./input/lendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-simulate_stalls=false
-system=system
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
-egid=100
-env=
-euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1347543 # Simulator instruction rate (inst/s)
-host_mem_usage 179988 # Number of bytes of host memory used
-host_seconds 65.56 # Real time elapsed on the host
-host_tick_rate 1347535 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 88340674 # Number of instructions simulated
-sim_seconds 0.000088 # Number of seconds simulated
-sim_ticks 88340673 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 88340674 # number of cpu cycles simulated
-system.cpu.num_insts 88340674 # Number of instructions executed
-system.cpu.num_refs 35224019 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := True
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 8
- sizeof(longaddr ) = 8
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 8
- sizeof(char * ) = 8
- ALLOC CORE_1 :: 16
- BHOOLE NATH
-
- OPEN File ./input/lendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 40054800
-
- OPEN File ./input/lendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-system=system
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
-egid=100
-env=
-euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 704446 # Simulator instruction rate (inst/s)
-host_mem_usage 275648 # Number of bytes of host memory used
-host_seconds 125.40 # Real time elapsed on the host
-host_tick_rate 9716991 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 88340674 # Number of instructions simulated
-sim_seconds 0.001219 # Number of seconds simulated
-sim_ticks 1218558003 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 34685672 # number of overall hits
-system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 204343 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 200247 # number of replacements
-system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use
-system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147714 # number of writebacks
-system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
-system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses
-system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 88264239 # number of overall hits
-system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses
-system.cpu.icache.overall_misses 76436 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 74391 # number of replacements
-system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use
-system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 259377 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 169116 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 135910 # number of replacements
-system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 115911 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1218558003 # number of cpu cycles simulated
-system.cpu.num_insts 88340674 # Number of instructions executed
-system.cpu.num_refs 35224019 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := True
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 8
- sizeof(longaddr ) = 8
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 8
- sizeof(char * ) = 8
- ALLOC CORE_1 :: 16
- BHOOLE NATH
-
- OPEN File ./input/lendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 40054800
-
- OPEN File ./input/lendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache fuPool icache l2cache toL2Bus workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+phase=0
+numThreads=1
+activity=0
+workload=system.cpu.workload
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 13202034 # Number of BTB hits
+global.BPredUnit.BTBLookups 22107115 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 30370 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 454360 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 16498204 # Number of conditional branches predicted
+global.BPredUnit.lookups 27047110 # Number of BP lookups
+global.BPredUnit.usedRAS 4878193 # Number of times the RAS was used to get a target.
+host_inst_rate 69520 # Simulator instruction rate (inst/s)
+host_mem_usage 239908 # Number of bytes of host memory used
+host_seconds 1144.87 # Real time elapsed on the host
+host_tick_rate 987535 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 14725847 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 11490673 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 28863760 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 16312214 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 79591756 # Number of instructions simulated
+sim_seconds 0.001131 # Number of seconds simulated
+sim_ticks 1130602014 # Number of ticks simulated
+system.cpu.commit.COM:branches 13754477 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 3893678 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 89505192
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 62882698 7025.59%
+ 1 8753972 978.04%
+ 2 5175203 578.20%
+ 3 3243621 362.39%
+ 4 2169519 242.39%
+ 5 1432847 160.09%
+ 6 1161882 129.81%
+ 7 791772 88.46%
+ 8 3893678 435.02%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 88340672 # Number of instructions committed
+system.cpu.commit.COM:loads 20379399 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 35224018 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 359967 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 21665941 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 79591756 # Number of Instructions Simulated
+system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
+system.cpu.cpi 14.205014 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 14.205014 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 19540231 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 4453.766964 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3237.815878 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 19382637 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 701886951 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.008065 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 157594 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 95950 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 199591922 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.003155 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 61644 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 4830.124895 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3999.409028 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 13942631 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 3239786953 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.045899 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 670746 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 527274 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 573803212 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 143472 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 3332.672727 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 3759.399862 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 162.470348 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 125901 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 366594 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 473312202 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 34153608 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 4758.521747 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 33325268 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 3941673904 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.024253 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 828340 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 623224 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 773395134 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.006006 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 205116 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 34153608 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 4758.521747 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 33325268 # number of overall hits
+system.cpu.dcache.overall_miss_latency 3941673904 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.024253 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 828340 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 623224 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 773395134 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.006006 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 205116 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 201020 # number of replacements
+system.cpu.dcache.sampled_refs 205116 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4057.039034 # Cycle average of tags in use
+system.cpu.dcache.total_refs 33325268 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 27784000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 147771 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 11948269 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 95198 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3558048 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 131593428 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 51674084 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 25481309 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 4702945 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 281359 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 401531 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 27047110 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 22733117 # Number of cache lines fetched
+system.cpu.fetch.Cycles 51481541 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 159026 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 148267180 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 3966980 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.287100 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 22733117 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 18080227 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.573826 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 94208138
+system.cpu.fetch.rateDist.min_value 0
+ 0 65459635 6948.41%
+ 1 1687117 179.08%
+ 2 1748812 185.63%
+ 3 1938924 205.81%
+ 4 6981531 741.08%
+ 5 6100701 647.58%
+ 6 758078 80.47%
+ 7 1979150 210.08%
+ 8 7554190 801.86%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 22733116 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3345.551905 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2359.548288 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 22631700 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 339292492 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.004461 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 101416 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 13878 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 206550138 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.003851 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 87538 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 3731.567010 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 258.538675 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 97 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 361962 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 22733116 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3345.551905 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency
+system.cpu.icache.demand_hits 22631700 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 339292492 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.004461 # miss rate for demand accesses
+system.cpu.icache.demand_misses 101416 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 13878 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 206550138 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.003851 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 87538 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 22733116 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3345.551905 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 22631700 # number of overall hits
+system.cpu.icache.overall_miss_latency 339292492 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.004461 # miss rate for overall accesses
+system.cpu.icache.overall_misses 101416 # number of overall misses
+system.cpu.icache.overall_mshr_hits 13878 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 206550138 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.003851 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 87538 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 85490 # number of replacements
+system.cpu.icache.sampled_refs 87537 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1835.330854 # Cycle average of tags in use
+system.cpu.icache.total_refs 22631700 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 1036393877 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 14379719 # Number of branches executed
+system.cpu.iew.EXEC:nop 9265977 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.989418 # Inst execution rate
+system.cpu.iew.EXEC:refs 43156162 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 15338261 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 46157981 # num instructions consuming a value
+system.cpu.iew.WB:count 86105601 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.741496 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 34225955 # num instructions producing a value
+system.cpu.iew.WB:rate 0.913993 # insts written-back per cycle
+system.cpu.iew.WB:sent 86171133 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 389534 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 3213991 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 28863760 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 4784 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1402526 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 16312214 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 110003367 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 27817901 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 453087 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 93211232 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 28742 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 12962 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 4702945 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 194395 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 1528 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 6922047 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 1365052 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 5008 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 3825 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1528 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 8484361 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1467595 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 3825 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 102872 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 286662 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.070398 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.070398 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 93664319 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 49995908 53.38% # Type of FU issued
+ IntMult 43196 0.05% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 123595 0.13% # Type of FU issued
+ FloatCmp 86 0.00% # Type of FU issued
+ FloatCvt 122386 0.13% # Type of FU issued
+ FloatMult 51 0.00% # Type of FU issued
+ FloatDiv 37853 0.04% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 27919833 29.81% # Type of FU issued
+ MemWrite 15421411 16.46% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 1229792 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013130 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 83895 6.82% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 589327 47.92% # attempts to use FU when none available
+ MemWrite 556570 45.26% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 94208138
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 54322746 5766.25%
+ 1 13333515 1415.33%
+ 2 10626230 1127.95%
+ 3 8813553 935.54%
+ 4 4440243 471.32%
+ 5 1597603 169.58%
+ 6 685526 72.77%
+ 7 334234 35.48%
+ 8 54488 5.78%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.994227 # Inst issue rate
+system.cpu.iq.iqInstsAdded 100732606 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 93664319 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 4784 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 20911338 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 73995 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 16334966 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 292646 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3929.598028 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2043.469607 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 122985 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 666699531 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.579748 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 169661 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 346697097 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579748 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 169661 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 147771 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 147307 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 1.593139 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 292646 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3929.598028 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 122985 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 666699531 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.579748 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 169661 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 346697097 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.579748 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 169661 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 440417 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3918.880417 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 270292 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 666699531 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.386282 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 170125 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 346697097 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.385228 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 169661 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 136892 # number of replacements
+system.cpu.l2cache.sampled_refs 169660 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 30349.297230 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 270292 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 625483000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 115938 # number of writebacks
+system.cpu.numCycles 94208138 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 7563765 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 87866 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 52361095 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 3315491 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 3509 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 154857350 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 130101763 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 82913656 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 25182526 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 4702945 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 3542613 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 30366775 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 855194 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 4773 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 6398047 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 4771 # count of temporary serializing insts renamed
+system.cpu.timesIdled 275758 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 40054800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1347543 # Simulator instruction rate (inst/s)
+host_mem_usage 179988 # Number of bytes of host memory used
+host_seconds 65.56 # Real time elapsed on the host
+host_tick_rate 1347535 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 88340674 # Number of instructions simulated
+sim_seconds 0.000088 # Number of seconds simulated
+sim_ticks 88340673 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 88340674 # number of cpu cycles simulated
+system.cpu.num_insts 88340674 # Number of instructions executed
+system.cpu.num_refs 35224019 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 40054800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 704446 # Simulator instruction rate (inst/s)
+host_mem_usage 275648 # Number of bytes of host memory used
+host_seconds 125.40 # Real time elapsed on the host
+host_tick_rate 9716991 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 88340674 # Number of instructions simulated
+sim_seconds 0.001219 # Number of seconds simulated
+sim_ticks 1218558003 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 34685672 # number of overall hits
+system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 204343 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 200247 # number of replacements
+system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use
+system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 147714 # number of writebacks
+system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
+system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses
+system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 88264239 # number of overall hits
+system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses
+system.cpu.icache.overall_misses 76436 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 74391 # number of replacements
+system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use
+system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 259377 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 169116 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 135910 # number of replacements
+system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 115911 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1218558003 # number of cpu cycles simulated
+system.cpu.num_insts 88340674 # Number of instructions executed
+system.cpu.num_refs 35224019 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 40054800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
m5.AddToPath('../configs/common')
from cpu2000 import vortex
-workload = vortex('alpha', 'tru64', 'smred')
+workload = vortex(isa, opsys, 'smred')
root.system.cpu.workload = workload.makeLiveProcess()
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-phase=0
-predType=tournament
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
-system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-phase=0
-numThreads=1
-activity=0
-workload=system.cpu.workload
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 1060300638 # Number of BTB hits
-global.BPredUnit.BTBLookups 1075264664 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 20658855 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1028649695 # Number of conditional branches predicted
-global.BPredUnit.lookups 1098978166 # Number of BP lookups
-global.BPredUnit.usedRAS 20738311 # Number of times the RAS was used to get a target.
-host_inst_rate 28281 # Simulator instruction rate (inst/s)
-host_mem_usage 1256892 # Number of bytes of host memory used
-host_seconds 61385.49 # Real time elapsed on the host
-host_tick_rate 405833 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 114920109 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 60881817 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 938731548 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 389309694 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1736043781 # Number of instructions simulated
-sim_seconds 0.024912 # Number of seconds simulated
-sim_ticks 24912272090 # Number of ticks simulated
-system.cpu.commit.COM:branches 214632552 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 72343657 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 5678957793
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 5103057521 8985.90%
- 1 193842571 341.33%
- 2 126727829 223.15%
- 3 63255233 111.39%
- 4 47590442 83.80%
- 5 34302037 60.40%
- 6 22774532 40.10%
- 7 15063971 26.53%
- 8 72343657 127.39%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 1819780126 # Number of instructions committed
-system.cpu.commit.COM:loads 445666361 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 606571343 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 20658355 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 3012390712 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 14.350025 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 14.350025 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 466176479 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5764.172372 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5678.042412 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 454097633 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 69624550394 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.025910 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 12078846 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 4784670 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 41416640690 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.015647 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7294176 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 157574910 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 35156809407 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.019621 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 3153592 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1270515 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 26783900812 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1883077 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 972.020892 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 2881.979981 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 66.650940 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 659829 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 896062 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 641367573 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 2582432746 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 626904981 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 6878.830546 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 611672543 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 104781359801 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.024298 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 15232438 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 6055185 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 68200541502 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.014639 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9177253 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 626904981 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 6878.830546 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 611672543 # number of overall hits
-system.cpu.dcache.overall_miss_latency 104781359801 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.024298 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 15232438 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 6055185 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 68200541502 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.014639 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9177253 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 9173157 # number of replacements
-system.cpu.dcache.sampled_refs 9177253 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4093.061614 # Cycle average of tags in use
-system.cpu.dcache.total_refs 611672543 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 39716000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2244715 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 3168036062 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 48557069 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 6641345328 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 1298412925 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 1202046298 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 501929792 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 1629 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 10462509 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 1098978166 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 541280485 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1955627258 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 11328270 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 7938391391 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 242391708 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.177803 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 541280485 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 1081038949 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.284345 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6180887586
-system.cpu.fetch.rateDist.min_value 0
- 0 4766540797 7711.74%
- 1 80764415 130.67%
- 2 63598055 102.89%
- 3 58203597 94.17%
- 4 424384465 686.61%
- 5 69131012 111.85%
- 6 94422767 152.77%
- 7 44649271 72.24%
- 8 579193207 937.07%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 541280484 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5378.819380 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4616.750831 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 541279194 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 6938677 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1290 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 387 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 4168926 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 4207.523810 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 599423.249169 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 21 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 88358 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 541280484 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5378.819380 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
-system.cpu.icache.demand_hits 541279194 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 6938677 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1290 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 387 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 4168926 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 541280484 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5378.819380 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 541279194 # number of overall hits
-system.cpu.icache.overall_miss_latency 6938677 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1290 # number of overall misses
-system.cpu.icache.overall_mshr_hits 387 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 4168926 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 716.132429 # Cycle average of tags in use
-system.cpu.icache.total_refs 541279194 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 18731384505 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 250098653 # Number of branches executed
-system.cpu.iew.EXEC:nop 147895912 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.440971 # Inst execution rate
-system.cpu.iew.EXEC:refs 918923683 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 177016651 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1839076786 # num instructions consuming a value
-system.cpu.iew.WB:count 2471794731 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.797100 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1465928228 # num instructions producing a value
-system.cpu.iew.WB:rate 0.399909 # insts written-back per cycle
-system.cpu.iew.WB:sent 2475054397 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 21956654 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 2471410228 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 938731548 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 111073783 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 389309694 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 4831881465 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 741907032 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 286170200 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 2725595031 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 1536928 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 161620 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 501929792 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 6153373 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 8 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 233590575 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 41593346 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 516978 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 47985 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 8 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 493065187 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 228404712 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 47985 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 726441 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 21230213 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.069686 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.069686 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 3011765231 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 0 0.00% # Type of FU issued
- IntAlu 1970711875 65.43% # Type of FU issued
- IntMult 679 0.00% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 206 0.00% # Type of FU issued
- FloatCmp 15 0.00% # Type of FU issued
- FloatCvt 146 0.00% # Type of FU issued
- FloatMult 12 0.00% # Type of FU issued
- FloatDiv 24 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 862446019 28.64% # Type of FU issued
- MemWrite 178606255 5.93% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 11307551 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.003754 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 509990 4.51% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 9173598 81.13% # attempts to use FU when none available
- MemWrite 1623963 14.36% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6180887586
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 4878979324 7893.65%
- 1 360055339 582.53%
- 2 481197713 778.53%
- 3 280796976 454.30%
- 4 94854448 153.46%
- 5 50760526 82.12%
- 6 26723872 43.24%
- 7 6795220 10.99%
- 8 724168 1.17%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 0.487271 # Inst issue rate
-system.cpu.iq.iqInstsAdded 4683985508 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 3011765231 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 2916477755 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 6096386 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 3050829124 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 9178154 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 7336.712513 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2076.036854 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 7008989 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 15914539999 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.236340 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 2169165 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4503266483 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 2169165 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2244715 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2215400 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.013060 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 29315 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.013060 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 29315 # number of Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.252507 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9178154 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 7336.712513 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 7008989 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 15914539999 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.236340 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 2169165 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 4503266483 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.236340 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 2169165 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 11422869 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 7238.883228 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 9224389 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 15914539999 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.192463 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 2198480 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 4503266483 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.189897 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 2169165 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 2136397 # number of replacements
-system.cpu.l2cache.sampled_refs 2169165 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 32623.472165 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 9224389 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 520424000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1039341 # number of writebacks
-system.cpu.numCycles 6180887586 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 2894504060 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 6511750 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 1451413065 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 266047107 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 3125053 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 8501370508 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 6112671585 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 4584914520 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1056218413 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 501929792 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 276756270 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 3208711557 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 65986 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 1117979447 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed
-system.cpu.timesIdled 7293390 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7006
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-simulate_stalls=false
-system=system
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-port=system.membus.port[0]
-
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 927424 # Simulator instruction rate (inst/s)
-host_mem_usage 144704 # Number of bytes of host memory used
-host_seconds 1962.19 # Real time elapsed on the host
-host_tick_rate 927424 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1819780129 # Number of instructions simulated
-sim_seconds 0.001820 # Number of seconds simulated
-sim_ticks 1819780128 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1819780129 # number of cpu cycles simulated
-system.cpu.num_insts 1819780129 # Number of instructions executed
-system.cpu.num_refs 606571345 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-system=system
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-port=system.membus.port[0]
-
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=bzip2 input.source 1
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 486900 # Simulator instruction rate (inst/s)
-host_mem_usage 1198232 # Number of bytes of host memory used
-host_seconds 3737.50 # Real time elapsed on the host
-host_tick_rate 8500130 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1819780129 # Number of instructions simulated
-sim_seconds 0.031769 # Number of seconds simulated
-sim_ticks 31769223012 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3121.340330 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2121.340330 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 22543612099 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 15321198099 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3602.533807 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.533807 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 6806339173 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 4917019173 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3221.115901 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 29349951272 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 20238217272 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3221.115901 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 596212431 # number of overall hits
-system.cpu.dcache.overall_miss_latency 29349951272 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 9111734 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 20238217272 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 9107638 # number of replacements
-system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4091.845274 # Cycle average of tags in use
-system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 75264000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2244708 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 4089.753117 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 3089.753117 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3279982 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 2477982 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2269051.531172 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 4089.753117 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3279982 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
-system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 2477982 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 4089.753117 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1819779328 # number of overall hits
-system.cpu.icache.overall_miss_latency 3279982 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
-system.cpu.icache.overall_misses 802 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 2477982 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 625.996248 # Cycle average of tags in use
-system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3215.890455 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1919.394872 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 6946815413 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4146186590 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244708 # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215611 # number of WriteReqNoAck|Writeback hits
-system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.012962 # miss rate for WriteReqNoAck|Writeback accesses
-system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29097 # number of WriteReqNoAck|Writeback misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.012962 # mshr miss rate for WriteReqNoAck|Writeback accesses
-system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29097 # number of WriteReqNoAck|Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3215.890455 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 6946815413 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 4146186590 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3173.148527 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 9167994 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 6946815413 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 2189250 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 4146186590 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 2127385 # number of replacements
-system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 32563.117941 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 748591000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1038202 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 31769223012 # number of cpu cycles simulated
-system.cpu.num_insts 1819780129 # Number of instructions executed
-system.cpu.num_refs 606571345 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-spec_init
-Loading Input Data
-Input data 1048576 bytes in length
-Compressing Input Data, level 7
-Compressed data 198546 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Compressing Input Data, level 9
-Compressed data 198677 bytes in length
-Uncompressing Data
-Uncompressed data 1048576 bytes in length
-Uncompressed data compared correctly
-Tested 1MB buffer: OK!
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
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+print_effaddr=true
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+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
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+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
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+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
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+text_file=m5stats.txt
+
+[system]
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+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache fuPool icache l2cache toL2Bus workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
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+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
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+decodeToRenameDelay=1
+decodeWidth=8
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+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
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+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
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+latency=1
+lifo=false
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+prefetch_miss=false
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+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
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+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
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+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
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+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
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+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
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+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
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+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
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+
+[system.cpu.fuPool.FUList6.opList1]
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+
+[system.cpu.fuPool.FUList7]
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+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
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+prioritizeRequests=false
+protocol=Null
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+size=131072
+split=false
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+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
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+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+phase=0
+numThreads=1
+activity=0
+workload=system.cpu.workload
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 1060300638 # Number of BTB hits
+global.BPredUnit.BTBLookups 1075264664 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 20658855 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1028649695 # Number of conditional branches predicted
+global.BPredUnit.lookups 1098978166 # Number of BP lookups
+global.BPredUnit.usedRAS 20738311 # Number of times the RAS was used to get a target.
+host_inst_rate 28281 # Simulator instruction rate (inst/s)
+host_mem_usage 1256892 # Number of bytes of host memory used
+host_seconds 61385.49 # Real time elapsed on the host
+host_tick_rate 405833 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 114920109 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 60881817 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 938731548 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 389309694 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1736043781 # Number of instructions simulated
+sim_seconds 0.024912 # Number of seconds simulated
+sim_ticks 24912272090 # Number of ticks simulated
+system.cpu.commit.COM:branches 214632552 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 72343657 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 5678957793
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 5103057521 8985.90%
+ 1 193842571 341.33%
+ 2 126727829 223.15%
+ 3 63255233 111.39%
+ 4 47590442 83.80%
+ 5 34302037 60.40%
+ 6 22774532 40.10%
+ 7 15063971 26.53%
+ 8 72343657 127.39%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 1819780126 # Number of instructions committed
+system.cpu.commit.COM:loads 445666361 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 606571343 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 20658355 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 3012390712 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
+system.cpu.cpi 14.350025 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 14.350025 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 466176479 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5764.172372 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5678.042412 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 454097633 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 69624550394 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.025910 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 12078846 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 4784670 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 41416640690 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.015647 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7294176 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 157574910 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 35156809407 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.019621 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 3153592 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1270515 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 26783900812 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1883077 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 972.020892 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 2881.979981 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 66.650940 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 659829 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 896062 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 641367573 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 2582432746 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 626904981 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 6878.830546 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 611672543 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 104781359801 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.024298 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 15232438 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 6055185 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 68200541502 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.014639 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9177253 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 626904981 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 6878.830546 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 611672543 # number of overall hits
+system.cpu.dcache.overall_miss_latency 104781359801 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.024298 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 15232438 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 6055185 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 68200541502 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.014639 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9177253 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 9173157 # number of replacements
+system.cpu.dcache.sampled_refs 9177253 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4093.061614 # Cycle average of tags in use
+system.cpu.dcache.total_refs 611672543 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 39716000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2244715 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 3168036062 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 48557069 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 6641345328 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 1298412925 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 1202046298 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 501929792 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1629 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 10462509 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 1098978166 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 541280485 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1955627258 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 11328270 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 7938391391 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 242391708 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.177803 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 541280485 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1081038949 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.284345 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 6180887586
+system.cpu.fetch.rateDist.min_value 0
+ 0 4766540797 7711.74%
+ 1 80764415 130.67%
+ 2 63598055 102.89%
+ 3 58203597 94.17%
+ 4 424384465 686.61%
+ 5 69131012 111.85%
+ 6 94422767 152.77%
+ 7 44649271 72.24%
+ 8 579193207 937.07%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 541280484 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5378.819380 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4616.750831 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 541279194 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 6938677 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1290 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 387 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 4168926 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 4207.523810 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 599423.249169 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 21 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 88358 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 541280484 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5378.819380 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
+system.cpu.icache.demand_hits 541279194 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 6938677 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1290 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 387 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 4168926 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 541280484 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5378.819380 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 541279194 # number of overall hits
+system.cpu.icache.overall_miss_latency 6938677 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1290 # number of overall misses
+system.cpu.icache.overall_mshr_hits 387 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 4168926 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 716.132429 # Cycle average of tags in use
+system.cpu.icache.total_refs 541279194 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 18731384505 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 250098653 # Number of branches executed
+system.cpu.iew.EXEC:nop 147895912 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.440971 # Inst execution rate
+system.cpu.iew.EXEC:refs 918923683 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 177016651 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 1839076786 # num instructions consuming a value
+system.cpu.iew.WB:count 2471794731 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.797100 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 1465928228 # num instructions producing a value
+system.cpu.iew.WB:rate 0.399909 # insts written-back per cycle
+system.cpu.iew.WB:sent 2475054397 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 21956654 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2471410228 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 938731548 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 111073783 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 389309694 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 4831881465 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 741907032 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 286170200 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2725595031 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 1536928 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 161620 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 501929792 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 6153373 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 8 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 233590575 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 41593346 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 516978 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 47985 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 8 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 493065187 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 228404712 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 47985 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 726441 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 21230213 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.069686 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.069686 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 3011765231 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 1970711875 65.43% # Type of FU issued
+ IntMult 679 0.00% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 206 0.00% # Type of FU issued
+ FloatCmp 15 0.00% # Type of FU issued
+ FloatCvt 146 0.00% # Type of FU issued
+ FloatMult 12 0.00% # Type of FU issued
+ FloatDiv 24 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 862446019 28.64% # Type of FU issued
+ MemWrite 178606255 5.93% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 11307551 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.003754 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 509990 4.51% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 9173598 81.13% # attempts to use FU when none available
+ MemWrite 1623963 14.36% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 6180887586
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 4878979324 7893.65%
+ 1 360055339 582.53%
+ 2 481197713 778.53%
+ 3 280796976 454.30%
+ 4 94854448 153.46%
+ 5 50760526 82.12%
+ 6 26723872 43.24%
+ 7 6795220 10.99%
+ 8 724168 1.17%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 0.487271 # Inst issue rate
+system.cpu.iq.iqInstsAdded 4683985508 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 3011765231 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 2916477755 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 6096386 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 3050829124 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 9178154 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 7336.712513 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2076.036854 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7008989 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 15914539999 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.236340 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2169165 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4503266483 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2169165 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2244715 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 2215400 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 0.013060 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 29315 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 0.013060 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 29315 # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 4.252507 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 9178154 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 7336.712513 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7008989 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 15914539999 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.236340 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 2169165 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 4503266483 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.236340 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 2169165 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 11422869 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 7238.883228 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 9224389 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 15914539999 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.192463 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 2198480 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 4503266483 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.189897 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 2169165 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 2136397 # number of replacements
+system.cpu.l2cache.sampled_refs 2169165 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 32623.472165 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 9224389 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 520424000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1039341 # number of writebacks
+system.cpu.numCycles 6180887586 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2894504060 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 6511750 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 1451413065 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 266047107 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 3125053 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 8501370508 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 6112671585 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 4584914520 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 1056218413 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 501929792 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 276756270 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 3208711557 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 65986 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 1117979447 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed
+system.cpu.timesIdled 7293390 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7006
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 927424 # Simulator instruction rate (inst/s)
+host_mem_usage 144704 # Number of bytes of host memory used
+host_seconds 1962.19 # Real time elapsed on the host
+host_tick_rate 927424 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1819780129 # Number of instructions simulated
+sim_seconds 0.001820 # Number of seconds simulated
+sim_ticks 1819780128 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1819780129 # number of cpu cycles simulated
+system.cpu.num_insts 1819780129 # Number of instructions executed
+system.cpu.num_refs 606571345 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 486900 # Simulator instruction rate (inst/s)
+host_mem_usage 1198232 # Number of bytes of host memory used
+host_seconds 3737.50 # Real time elapsed on the host
+host_tick_rate 8500130 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1819780129 # Number of instructions simulated
+sim_seconds 0.031769 # Number of seconds simulated
+sim_ticks 31769223012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3121.340330 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2121.340330 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 22543612099 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 15321198099 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3602.533807 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.533807 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 6806339173 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 4917019173 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3221.115901 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29349951272 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 20238217272 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3221.115901 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 596212431 # number of overall hits
+system.cpu.dcache.overall_miss_latency 29349951272 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9111734 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 20238217272 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 9107638 # number of replacements
+system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4091.845274 # Cycle average of tags in use
+system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 75264000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2244708 # number of writebacks
+system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4089.753117 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3089.753117 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 3279982 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 2477982 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 2269051.531172 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4089.753117 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 3279982 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 2477982 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4089.753117 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1819779328 # number of overall hits
+system.cpu.icache.overall_miss_latency 3279982 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.overall_misses 802 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 2477982 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 625.996248 # Cycle average of tags in use
+system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3215.890455 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1919.394872 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 6946815413 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4146186590 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244708 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215611 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.012962 # miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29097 # number of WriteReqNoAck|Writeback misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.012962 # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29097 # number of WriteReqNoAck|Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3215.890455 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 6946815413 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 4146186590 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3173.148527 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 9167994 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 6946815413 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 2189250 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 4146186590 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 2127385 # number of replacements
+system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 32563.117941 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 748591000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1038202 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 31769223012 # number of cpu cycles simulated
+system.cpu.num_insts 1819780129 # Number of instructions executed
+system.cpu.num_refs 606571345 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
m5.AddToPath('../configs/common')
from cpu2000 import bzip2_source
-workload = bzip2_source('alpha', 'tru64', 'lgred')
+workload = bzip2_source(isa, opsys, 'lgred')
root.system.cpu.workload = workload.makeLiveProcess()
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-phase=0
-predType=tournament
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
-system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing
-egid=100
-env=
-euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-phase=0
-numThreads=1
-activity=0
-workload=system.cpu.workload
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 11848811 # Number of BTB hits
-global.BPredUnit.BTBLookups 15227898 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1227 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 2015952 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 12943595 # Number of conditional branches predicted
-global.BPredUnit.lookups 17560137 # Number of BP lookups
-global.BPredUnit.usedRAS 1685355 # Number of times the RAS was used to get a target.
-host_inst_rate 110871 # Simulator instruction rate (inst/s)
-host_mem_usage 184176 # Number of bytes of host memory used
-host_seconds 759.26 # Real time elapsed on the host
-host_tick_rate 138735 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 9867030 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 3328836 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 29553768 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 9396457 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 84179709 # Number of instructions simulated
-sim_seconds 0.000105 # Number of seconds simulated
-sim_ticks 105335101 # Number of ticks simulated
-system.cpu.commit.COM:branches 10240685 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3300349 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 65617496
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 32041205 4883.03%
- 1 13628356 2076.94%
- 2 7878182 1200.62%
- 3 3859920 588.25%
- 4 2040157 310.92%
- 5 1456623 221.99%
- 6 796888 121.44%
- 7 615816 93.85%
- 8 3300349 502.97%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 91903055 # Number of instructions committed
-system.cpu.commit.COM:loads 20034413 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 26537108 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 2003468 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 39205061 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 84179709 # Number of Instructions Simulated
-system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
-system.cpu.cpi 1.251312 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.251312 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 23022109 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5495.207331 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4910.485944 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 23021236 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4797316 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 873 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 375 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2445422 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4880.722363 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4578.932720 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6495178 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 28918280 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000911 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 5925 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 4186 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 7962764 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 2807.125000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 3125.260571 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13194.641931 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 8 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 875 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 22457 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 2734603 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 29523212 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4959.634598 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 29516414 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 33715596 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 6798 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 4561 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10408186 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2237 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 29523212 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4959.634598 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 29516414 # number of overall hits
-system.cpu.dcache.overall_miss_latency 33715596 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 6798 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 4561 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10408186 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2237 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 158 # number of replacements
-system.cpu.dcache.sampled_refs 2237 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1400.647488 # Cycle average of tags in use
-system.cpu.dcache.total_refs 29516414 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 105 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 2047370 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 12661 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 2829477 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 146297095 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 36266329 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 27223403 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 6075840 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 45354 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 80395 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 17560137 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 17576948 # Number of cache lines fetched
-system.cpu.fetch.Cycles 45711428 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 479088 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 150837354 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 2061309 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.244934 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 17576948 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 13534166 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.103924 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 71693337
-system.cpu.fetch.rateDist.min_value 0
- 0 43559639 6075.83%
- 1 2788432 388.94%
- 2 2133609 297.60%
- 3 3200202 446.37%
- 4 4098889 571.73%
- 5 1363717 190.22%
- 6 1885995 263.06%
- 7 1651845 230.40%
- 8 11011009 1535.85%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 17576948 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3407.568545 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2506.978423 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 17563424 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 46083957 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000769 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 13524 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 3467 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 25212682 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 10057 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 3513.269231 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1746.387988 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 26 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 91345 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 17576948 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3407.568545 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency
-system.cpu.icache.demand_hits 17563424 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 46083957 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000769 # miss rate for demand accesses
-system.cpu.icache.demand_misses 13524 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 3467 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 25212682 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 10057 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 17576948 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3407.568545 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 17563424 # number of overall hits
-system.cpu.icache.overall_miss_latency 46083957 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000769 # miss rate for overall accesses
-system.cpu.icache.overall_misses 13524 # number of overall misses
-system.cpu.icache.overall_mshr_hits 3467 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 25212682 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 10057 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 8145 # number of replacements
-system.cpu.icache.sampled_refs 10057 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1487.085502 # Cycle average of tags in use
-system.cpu.icache.total_refs 17563424 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 33641765 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 12581618 # Number of branches executed
-system.cpu.iew.EXEC:nop 11617565 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.388001 # Inst execution rate
-system.cpu.iew.EXEC:refs 31473535 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 7134398 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 88408054 # num instructions consuming a value
-system.cpu.iew.WB:count 97920299 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.731090 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 64634219 # num instructions producing a value
-system.cpu.iew.WB:rate 1.365821 # insts written-back per cycle
-system.cpu.iew.WB:sent 98494929 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2154192 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 104376 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 29553768 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 2191495 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 9396457 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 131107086 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 24339137 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2193063 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 99510422 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 16363 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 879 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 6075840 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 34734 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 9915 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 36009 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 941599 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 3004 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 23070 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 9915 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 9519355 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 2893762 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 23070 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 196104 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1958088 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.799161 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.799161 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 101703485 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 7 0.00% # Type of FU issued
- IntAlu 62578225 61.53% # Type of FU issued
- IntMult 472394 0.46% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2776755 2.73% # Type of FU issued
- FloatCmp 115486 0.11% # Type of FU issued
- FloatCvt 2376016 2.34% # Type of FU issued
- FloatMult 302348 0.30% # Type of FU issued
- FloatDiv 754954 0.74% # Type of FU issued
- FloatSqrt 321 0.00% # Type of FU issued
- MemRead 25019338 24.60% # Type of FU issued
- MemWrite 7307641 7.19% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 1392706 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013694 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
-(null) 0 0.00% # attempts to use FU when none available
-IntAlu 193189 13.87% # attempts to use FU when none available
-IntMult 0 0.00% # attempts to use FU when none available
-IntDiv 0 0.00% # attempts to use FU when none available
-FloatAdd 1883 0.14% # attempts to use FU when none available
-FloatCmp 96 0.01% # attempts to use FU when none available
-FloatCvt 2836 0.20% # attempts to use FU when none available
-FloatMult 2464 0.18% # attempts to use FU when none available
-FloatDiv 659899 47.38% # attempts to use FU when none available
-FloatSqrt 0 0.00% # attempts to use FU when none available
-MemRead 465101 33.40% # attempts to use FU when none available
-MemWrite 67238 4.83% # attempts to use FU when none available
-IprAccess 0 0.00% # attempts to use FU when none available
-InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 71693337
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 27977053 3902.32%
- 1 15408153 2149.18%
- 2 12854527 1792.99%
- 3 7056557 984.27%
- 4 4494209 626.87%
- 5 2427532 338.60%
- 6 1097338 153.06%
- 7 305661 42.63%
- 8 72307 10.09%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.418590 # Inst issue rate
-system.cpu.iq.iqInstsAdded 119489085 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 101703485 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 34413373 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 132312 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 28441004 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 12293 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3855.809345 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2071.040418 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 19556665 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.412593 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 5072 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 10504317 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.412593 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 5072 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.444401 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 12293 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3855.809345 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 19556665 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.412593 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 5072 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 10504317 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.412593 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 5072 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 12398 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3855.809345 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 7326 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 19556665 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.409098 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 5072 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 10504317 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.409098 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 5072 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 5072 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3261.872945 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7326 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 71693337 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 812700 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 369396 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 37208342 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 772307 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 122 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 182866276 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 141908898 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 104156212 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 26334995 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 6075840 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1200845 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 35728851 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 60615 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 555 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 2896644 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 544 # count of temporary serializing insts renamed
-system.cpu.timesIdled 10380 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
+++ /dev/null
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
+++ /dev/null
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
+++ /dev/null
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
+++ /dev/null
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
+++ /dev/null
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124
\ No newline at end of file
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-simulate_stalls=false
-system=system
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1013473 # Simulator instruction rate (inst/s)
-host_mem_usage 151596 # Number of bytes of host memory used
-host_seconds 90.68 # Real time elapsed on the host
-host_tick_rate 1013469 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 91903057 # Number of instructions simulated
-sim_seconds 0.000092 # Number of seconds simulated
-sim_ticks 91903056 # Number of ticks simulated
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 91903057 # number of cpu cycles simulated
-system.cpu.num_insts 91903057 # Number of instructions executed
-system.cpu.num_refs 26537109 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
+++ /dev/null
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
+++ /dev/null
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
+++ /dev/null
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
+++ /dev/null
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
+++ /dev/null
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124
\ No newline at end of file
+++ /dev/null
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-system=system
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
-egid=100
-env=
-euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
+++ /dev/null
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 607322 # Simulator instruction rate (inst/s)
-host_mem_usage 157212 # Number of bytes of host memory used
-host_seconds 151.33 # Real time elapsed on the host
-host_tick_rate 1013960 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 91903057 # Number of instructions simulated
-sim_seconds 0.000153 # Number of seconds simulated
-sim_ticks 153438012 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3701.356540 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2701.356540 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1754443 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1280443 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3869.070366 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2869.070366 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 6763135 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5015135 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3833.293429 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8517578 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 6295578 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3833.293429 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 26495079 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8517578 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2222 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 6295578 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 157 # number of replacements
-system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1398.130089 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 104 # number of writebacks
-system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3117.603760 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2117.603760 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 26530808 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 18020808 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 10798.419271 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3117.603760 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency
-system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 26530808 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
-system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 18020808 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3117.603760 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 91894548 # number of overall hits
-system.cpu.icache.overall_miss_latency 26530808 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
-system.cpu.icache.overall_misses 8510 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 18020808 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 6681 # number of replacements
-system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1374.520503 # Cycle average of tags in use
-system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2892.483207 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1885.503778 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 13779790 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 8982540 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.274559 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2892.483207 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 13779790 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 8982540 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2892.483207 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 6072 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 13779790 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 4764 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 8982540 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3073.845977 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 153438012 # number of cpu cycles simulated
-system.cpu.num_insts 91903057 # Number of instructions executed
-system.cpu.num_refs 26537109 # Number of memory references
-system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
-
----------- End Simulation Statistics ----------
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
+++ /dev/null
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
+++ /dev/null
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
+++ /dev/null
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
+++ /dev/null
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
+++ /dev/null
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
+++ /dev/null
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0. Starting simulation...
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124
\ No newline at end of file
--- /dev/null
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+
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+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing
+egid=100
+env=
+euid=100
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+phase=0
+numThreads=1
+activity=0
+workload=system.cpu.workload
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 11848811 # Number of BTB hits
+global.BPredUnit.BTBLookups 15227898 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1227 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 2015952 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 12943595 # Number of conditional branches predicted
+global.BPredUnit.lookups 17560137 # Number of BP lookups
+global.BPredUnit.usedRAS 1685355 # Number of times the RAS was used to get a target.
+host_inst_rate 110871 # Simulator instruction rate (inst/s)
+host_mem_usage 184176 # Number of bytes of host memory used
+host_seconds 759.26 # Real time elapsed on the host
+host_tick_rate 138735 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 9867030 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 3328836 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 29553768 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 9396457 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 84179709 # Number of instructions simulated
+sim_seconds 0.000105 # Number of seconds simulated
+sim_ticks 105335101 # Number of ticks simulated
+system.cpu.commit.COM:branches 10240685 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 3300349 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 65617496
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 32041205 4883.03%
+ 1 13628356 2076.94%
+ 2 7878182 1200.62%
+ 3 3859920 588.25%
+ 4 2040157 310.92%
+ 5 1456623 221.99%
+ 6 796888 121.44%
+ 7 615816 93.85%
+ 8 3300349 502.97%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 91903055 # Number of instructions committed
+system.cpu.commit.COM:loads 20034413 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 26537108 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 2003468 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 39205061 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 84179709 # Number of Instructions Simulated
+system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
+system.cpu.cpi 1.251312 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.251312 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 23022109 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5495.207331 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4910.485944 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 23021236 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4797316 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 873 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 375 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2445422 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 4880.722363 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4578.932720 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6495178 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 28918280 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000911 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 5925 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 4186 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 7962764 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 2807.125000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 3125.260571 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 13194.641931 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 8 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 875 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 22457 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 2734603 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 29523212 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 4959.634598 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 29516414 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 33715596 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 6798 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 4561 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 10408186 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2237 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 29523212 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 4959.634598 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 29516414 # number of overall hits
+system.cpu.dcache.overall_miss_latency 33715596 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 6798 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 4561 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 10408186 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2237 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 158 # number of replacements
+system.cpu.dcache.sampled_refs 2237 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 1400.647488 # Cycle average of tags in use
+system.cpu.dcache.total_refs 29516414 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 105 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 2047370 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 12661 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 2829477 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 146297095 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 36266329 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 27223403 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 6075840 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 45354 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 80395 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 17560137 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 17576948 # Number of cache lines fetched
+system.cpu.fetch.Cycles 45711428 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 479088 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 150837354 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 2061309 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.244934 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 17576948 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 13534166 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.103924 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 71693337
+system.cpu.fetch.rateDist.min_value 0
+ 0 43559639 6075.83%
+ 1 2788432 388.94%
+ 2 2133609 297.60%
+ 3 3200202 446.37%
+ 4 4098889 571.73%
+ 5 1363717 190.22%
+ 6 1885995 263.06%
+ 7 1651845 230.40%
+ 8 11011009 1535.85%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 17576948 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3407.568545 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2506.978423 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 17563424 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 46083957 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000769 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 13524 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 3467 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 25212682 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10057 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 3513.269231 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1746.387988 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 26 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 91345 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 17576948 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3407.568545 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency
+system.cpu.icache.demand_hits 17563424 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 46083957 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000769 # miss rate for demand accesses
+system.cpu.icache.demand_misses 13524 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 3467 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 25212682 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10057 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 17576948 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3407.568545 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 17563424 # number of overall hits
+system.cpu.icache.overall_miss_latency 46083957 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000769 # miss rate for overall accesses
+system.cpu.icache.overall_misses 13524 # number of overall misses
+system.cpu.icache.overall_mshr_hits 3467 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 25212682 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 10057 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 8145 # number of replacements
+system.cpu.icache.sampled_refs 10057 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1487.085502 # Cycle average of tags in use
+system.cpu.icache.total_refs 17563424 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 33641765 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 12581618 # Number of branches executed
+system.cpu.iew.EXEC:nop 11617565 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.388001 # Inst execution rate
+system.cpu.iew.EXEC:refs 31473535 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 7134398 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 88408054 # num instructions consuming a value
+system.cpu.iew.WB:count 97920299 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.731090 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 64634219 # num instructions producing a value
+system.cpu.iew.WB:rate 1.365821 # insts written-back per cycle
+system.cpu.iew.WB:sent 98494929 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2154192 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 104376 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 29553768 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 2191495 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 9396457 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 131107086 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 24339137 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2193063 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 99510422 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 16363 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 879 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 6075840 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 34734 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 9915 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 36009 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 941599 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 3004 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 23070 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 9915 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 9519355 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 2893762 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 23070 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 196104 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1958088 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.799161 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.799161 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 101703485 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 7 0.00% # Type of FU issued
+ IntAlu 62578225 61.53% # Type of FU issued
+ IntMult 472394 0.46% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2776755 2.73% # Type of FU issued
+ FloatCmp 115486 0.11% # Type of FU issued
+ FloatCvt 2376016 2.34% # Type of FU issued
+ FloatMult 302348 0.30% # Type of FU issued
+ FloatDiv 754954 0.74% # Type of FU issued
+ FloatSqrt 321 0.00% # Type of FU issued
+ MemRead 25019338 24.60% # Type of FU issued
+ MemWrite 7307641 7.19% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 1392706 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013694 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+(null) 0 0.00% # attempts to use FU when none available
+IntAlu 193189 13.87% # attempts to use FU when none available
+IntMult 0 0.00% # attempts to use FU when none available
+IntDiv 0 0.00% # attempts to use FU when none available
+FloatAdd 1883 0.14% # attempts to use FU when none available
+FloatCmp 96 0.01% # attempts to use FU when none available
+FloatCvt 2836 0.20% # attempts to use FU when none available
+FloatMult 2464 0.18% # attempts to use FU when none available
+FloatDiv 659899 47.38% # attempts to use FU when none available
+FloatSqrt 0 0.00% # attempts to use FU when none available
+MemRead 465101 33.40% # attempts to use FU when none available
+MemWrite 67238 4.83% # attempts to use FU when none available
+IprAccess 0 0.00% # attempts to use FU when none available
+InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 71693337
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 27977053 3902.32%
+ 1 15408153 2149.18%
+ 2 12854527 1792.99%
+ 3 7056557 984.27%
+ 4 4494209 626.87%
+ 5 2427532 338.60%
+ 6 1097338 153.06%
+ 7 305661 42.63%
+ 8 72307 10.09%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.418590 # Inst issue rate
+system.cpu.iq.iqInstsAdded 119489085 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 101703485 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 34413373 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 132312 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 28441004 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 12293 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3855.809345 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2071.040418 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 19556665 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.412593 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 5072 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 10504317 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.412593 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 5072 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 1.444401 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 12293 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3855.809345 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 19556665 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.412593 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 5072 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 10504317 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.412593 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 5072 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 12398 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3855.809345 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 7326 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 19556665 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.409098 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 5072 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 10504317 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.409098 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 5072 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 5072 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 3261.872945 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7326 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 71693337 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 812700 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 369396 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 37208342 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 772307 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 122 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 182866276 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 141908898 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 104156212 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 26334995 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 6075840 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1200845 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 35728851 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 60615 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 555 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 2896644 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 544 # count of temporary serializing insts renamed
+system.cpu.timesIdled 10380 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
--- /dev/null
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
--- /dev/null
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
--- /dev/null
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
--- /dev/null
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
--- /dev/null
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124
\ No newline at end of file
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 1013473 # Simulator instruction rate (inst/s)
+host_mem_usage 151596 # Number of bytes of host memory used
+host_seconds 90.68 # Real time elapsed on the host
+host_tick_rate 1013469 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 91903057 # Number of instructions simulated
+sim_seconds 0.000092 # Number of seconds simulated
+sim_ticks 91903056 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 91903057 # number of cpu cycles simulated
+system.cpu.num_insts 91903057 # Number of instructions executed
+system.cpu.num_refs 26537109 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
--- /dev/null
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
--- /dev/null
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
--- /dev/null
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
--- /dev/null
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
--- /dev/null
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124
\ No newline at end of file
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[statsreset]
+reset_cycle=0
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 607322 # Simulator instruction rate (inst/s)
+host_mem_usage 157212 # Number of bytes of host memory used
+host_seconds 151.33 # Real time elapsed on the host
+host_tick_rate 1013960 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 91903057 # Number of instructions simulated
+sim_seconds 0.000153 # Number of seconds simulated
+sim_ticks 153438012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3701.356540 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2701.356540 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 1754443 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 1280443 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3869.070366 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2869.070366 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 6763135 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5015135 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3833.293429 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8517578 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 6295578 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3833.293429 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 26495079 # number of overall hits
+system.cpu.dcache.overall_miss_latency 8517578 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2222 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 6295578 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 157 # number of replacements
+system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 1398.130089 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 104 # number of writebacks
+system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3117.603760 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2117.603760 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 26530808 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 18020808 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 10798.419271 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3117.603760 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency
+system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 26530808 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
+system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 18020808 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3117.603760 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 91894548 # number of overall hits
+system.cpu.icache.overall_miss_latency 26530808 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
+system.cpu.icache.overall_misses 8510 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 18020808 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 6681 # number of replacements
+system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1374.520503 # Cycle average of tags in use
+system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2892.483207 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1885.503778 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 13779790 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 8982540 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 1.274559 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2892.483207 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 13779790 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 8982540 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2892.483207 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 6072 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 13779790 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 4764 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 8982540 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 3073.845977 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 153438012 # number of cpu cycles simulated
+system.cpu.num_insts 91903057 # Number of instructions executed
+system.cpu.num_refs 26537109 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
--- /dev/null
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
--- /dev/null
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
--- /dev/null
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
--- /dev/null
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
--- /dev/null
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
--- /dev/null
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124
\ No newline at end of file
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+dummy=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+input=cin
+output=cout
+env=
+cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 676464 # Simulator instruction rate (inst/s)
+host_mem_usage 149916 # Number of bytes of host memory used
+host_seconds 285.95 # Real time elapsed on the host
+host_tick_rate 676463 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 193435973 # Number of instructions simulated
+sim_seconds 0.000193 # Number of seconds simulated
+sim_ticks 193435972 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 193435973 # number of cpu cycles simulated
+system.cpu.num_insts 193435973 # Number of instructions executed
+system.cpu.num_refs 76732959 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 396 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
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+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
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+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
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+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
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+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
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+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
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+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
--- /dev/null
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
--- /dev/null
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
--- /dev/null
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
--- /dev/null
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
--- /dev/null
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
--- /dev/null
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x11e394 length 0x10.
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x0 length 0x0.
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0. Starting simulation...
+warn: Ignoring request to flush register windows.
+warn: Increasing stack size by one page.
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Mar 12 2007 16:53:49
+M5 started Mon Mar 12 17:37:07 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+Exiting @ tick 193435972 because target called exit()
from cpu2000 import twolf
import os
-workload = twolf('alpha', 'tru64', 'smred')
+workload = twolf(isa, opsys, 'smred')
root.system.cpu.workload = workload.makeLiveProcess()
cwd = root.system.cpu.workload.cwd
projects / gem5.git / commitdiff