(no commit message)

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 958c63f6fa4dbcb87c39f36e08013432295ba064..6d2a59f0f62f4281ac59c3c6d361e21521288b85 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -35,11 +35,6 @@ Notes:
 
 ## Mask-suited Bitmanipulation
 
-Based on RVV masked set-before-first, set-after-first etc.
-and Intel and AMD Bitmanip instructions made generalised then
-advanced further to include masks, this is a single instruction
-covering 24 individual instructions in other ISAs.
-*(sbf/sof/sif moved to [[discussion]])*
 
 BM2-Form
 
@@ -49,35 +44,6 @@ BM2-Form
 
 * bmask RS,RA,RB,bm,L
 
-The patterns within the pseudocode for AMD TBM and x86 BMI1 are
-as follows:
-
-* first pattern A: two options `x` or `~x`
-* second pattern B: three options `|` `&` or `^`
-* third pattern C: four options `x+1`, `x-1`, `~(x+1)` or `(~x)+1`
-
-Thus it makes sense to create a single instruction
-that covers all of these.  A crucial addition that is essential
-for Scalable Vector usage as Predicate Masks, is the second mask parameter
-(RB).  The additional paramater, L, if set, will leave bits of RA masked
-by RB unaltered, otherwise those bits are set to zero. Note that when `RB=0`
-then instead of reading from the register file the mask is set to all ones.
-
-The lower two bits of `bm` set to 0b11 are `RESERVED`. An illegal instruction
-trap must be raised.
-
-Executable pseudocode demo:
-
-```
-[[!inline pages="openpower/sv/bmask.py" quick="yes" raw="yes" ]]
-```
-
-
-
-BM2-Form
-
-* bmask  RT,RA,RB,bm,L
-
 Pseudo-code:
 
 ```
@@ -107,9 +73,19 @@ Pseudo-code:
     RT <- result
 ```
 
+* first pattern A: two options `x` or `~x`
+* second pattern B: three options `|` `&` or `^`
+* third pattern C: four options `x+1`, `x-1`, `~(x+1)` or `(~x)+1`
+
+
+The lower two bits of `bm` set to 0b11 are `RESERVED`. An illegal instruction
+trap must be raised.
+
 Special Registers Altered:
 
+```
     None
+```
 
 ## Carry-lookahead