[PATCH][AArch64] Allow CMP+SHIFT when comparing with zero

gcc/

	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for
	comparision with zero.

gcc/testsuite/

	* gcc.target/aarch64/cmp_shifted_reg_1.c: New.

From-SVN: r248836

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 079f1fd61f091760f0c50dbba36b3ee7f9a3870d..070bb8f6db5e60c094cb257067547988184b4d10 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-06-02  Sudakshina Das  <sudi.das@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for
+       comparision with zero.
+
 2017-06-02  Will Schmidt  <will_schmidt@vnet.ibm.com>
        * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling
        for early expansion of vec_min and vec_max builtins.

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 7064f050a107b3481a1a8ae5315de27584ee5ade..5707e5317e2a11f3ed7b9620f96e4acf92b0557c 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4767,7 +4767,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
      the comparison will have to be swapped when we emit the assembly
      code.  */
   if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
-      && (REG_P (y) || GET_CODE (y) == SUBREG)
+      && (REG_P (y) || GET_CODE (y) == SUBREG || y == const0_rtx)
       && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
          || GET_CODE (x) == LSHIFTRT
          || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND))

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 70a8335d5df66e4a16b32d414ff81376858ca2aa..2f38470c9d17d964a6f5b0325c8ad1e3c6ab98b0 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2017-06-02  Sudakshina Das  <sudi.das@arm.com>
+
+       * gcc.target/aarch64/cmp_shifted_reg_1.c: New.
+
 2017-06-02  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
        * gcc.target/powerpc/fold-vec-minmax-char.c: New.

diff --git a/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c b/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c
new file mode 100644 (file)
index 0000000..cacecf4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 " } */
+
+int f3 (int x, int y)
+{
+  int res = x << 3;
+  return res != 0;
+}
+
+/* We should combine the shift and compare */
+/* { dg-final { scan-assembler "cmp\.*\twzr, w\[0-9\]+, lsl 3" } } */