litesata/example_designs: Add missing clock in phy instantiation

diff --git a/misoclib/mem/litesata/example_designs/targets/core.py b/misoclib/mem/litesata/example_designs/targets/core.py
index d841d4ecd944a6114fdd8f994c8c30d28da917d2..e15b259a83b33718529e3ddd58944bc7c43a9f6d 100644 (file)
--- a/misoclib/mem/litesata/example_designs/targets/core.py
+++ b/misoclib/mem/litesata/example_designs/targets/core.py
@@ -17,7 +17,7 @@ class Core(Module):
         self.clk_freq = clk_freq
 
         # SATA PHY/Core/Frontend
-        self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
+        self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sys_clk"), platform.request("sata"), "sata_gen2", clk_freq)
         self.submodules.sata_core = LiteSATACore(self.sata_phy)
         self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)