processor_t unfriends gdbserver_t.

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 7130364b8f7ba163cd7d575eedba64491b14cfe9..ca58ee475473dd53043e074ab3e253c7c63cb2f7 100755 (executable)
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -95,7 +95,7 @@ save_128:
 spontaneous_halt:
         csrr    s0, CSR_MHARTID
         sw      s0, SETHALTNOT(zero)
-        csrsi   DCSR, DCSR_HALT_OFFSET
+        csrsi   DCSR, (1<<DCSR_HALT_OFFSET)
 
 wait_for_interrupt:
         csrr    s0, DCSR

diff --git a/debug_rom/debug_rom.h b/debug_rom/debug_rom.h
index 79162c2e140837093b9b7093a4ad832d0d4f3757..6fef9481567ea4c8e1c8fb51338065cfa115b5da 100644 (file)
--- a/debug_rom/debug_rom.h
+++ b/debug_rom/debug_rom.h
@@ -11,7 +11,7 @@ static const unsigned char debug_rom_raw[] = {
   0x63, 0x46, 0x04, 0x00, 0x23, 0x2e, 0x90, 0xc2, 0x67, 0x00, 0x00, 0xc0,
   0x13, 0x14, 0x14, 0x00, 0x63, 0x46, 0x04, 0x00, 0x23, 0x3c, 0x90, 0xc2,
   0x67, 0x00, 0x00, 0xc0, 0x13, 0x00, 0x00, 0x00, 0x67, 0x00, 0x00, 0xc0,
-  0x73, 0x24, 0x50, 0xf1, 0x23, 0x20, 0x80, 0xf0, 0x73, 0xe0, 0x01, 0x79,
+  0x73, 0x24, 0x50, 0xf1, 0x23, 0x20, 0x80, 0xf0, 0x73, 0x60, 0x04, 0x79,
   0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x04, 0x40, 0xe3, 0x0c, 0x04, 0xfe,
   0x6f, 0xf0, 0x1f, 0xfc
 };

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 25d1d51f2aa5507b96048d1491e1c4ca70f98961..ae4c9597a1bd00af5b9ecfd992c470c807659d66 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -61,9 +61,9 @@ void processor_t::step(size_t n)
   }
 
   if (state.dcsr.cause != DCSR_CAUSE_NONE) {
-    // In Debug Mode, just do 100 steps at a time. Otherwise we're going to be
+    // In Debug Mode, just do 10 steps at a time. Otherwise we're going to be
     // spinning the rest of the time anyway.
-    n = std::max(n, (size_t) 100);
+    n = std::max(n, (size_t) 10);
   }
 
   while (n > 0) {

diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc
index a460b67daab55df049059eb2432065c17bb1623b..04879394632a00590430d58033d29f706618df80 100644 (file)
--- a/riscv/gdbserver.cc
+++ b/riscv/gdbserver.cc
@@ -178,13 +178,13 @@ uint32_t gdbserver_t::read_debug_ram(unsigned int index)
 void gdbserver_t::halt()
 {
   processor_t *p = sim->get_core(0);
-  write_debug_ram(0, csrsi(DCSR_ADDRESS, DCSR_HALT_OFFSET));
+  write_debug_ram(0, csrsi(DCSR_ADDRESS, DCSR_HALT_MASK));
   write_debug_ram(1, csrr(S0, DPC_ADDRESS));
   write_debug_ram(2, sw(S0, 0, (uint16_t) DEBUG_RAM_START));
   write_debug_ram(3, csrr(S0, DCSR_ADDRESS));
   write_debug_ram(4, sw(S0, 0, (uint16_t) DEBUG_RAM_START + 8));
   write_debug_ram(5, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*5))));
-  sim->debug_module.set_interrupt(p->id);
+  sim->debug_module.set_interrupt(0);
   state = STATE_HALTING;
 }
 
@@ -356,6 +356,12 @@ void gdbserver_t::handle_halt_reason(const std::vector<uint8_t> &packet)
   send_packet("S00");
 }
 
+void die(const char* msg)
+{
+  fprintf(stderr, "%s\n", msg);
+  abort();
+}
+
 void gdbserver_t::handle_general_registers_read(const std::vector<uint8_t> &packet)
 {
   // Register order that gdb expects is:
@@ -374,7 +380,8 @@ void gdbserver_t::handle_general_registers_read(const std::vector<uint8_t> &pack
   running_checksum = 0;
   processor_t *p = sim->get_core(0);
   for (int r = 0; r < 32; r++) {
-    send(p->state.XPR[r]);
+    die("handle_general_registers_read");
+    // send(p->state.XPR[r]);
   }
   send_running_checksum();
   expect_ack = true;
@@ -457,6 +464,8 @@ void gdbserver_t::handle_register_read(const std::vector<uint8_t> &packet)
   send("$");
   running_checksum = 0;
 
+  die("handle_register_read");
+  /*
   if (n >= REG_XPR0 && n <= REG_XPR31) {
     send(p->state.XPR[n - REG_XPR0]);
   } else if (n == REG_PC) {
@@ -475,6 +484,7 @@ void gdbserver_t::handle_register_read(const std::vector<uint8_t> &packet)
   } else {
     return send_packet("E02");
   }
+  */
 
   send_running_checksum();
   expect_ack = true;
@@ -496,6 +506,8 @@ void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet)
 
   processor_t *p = sim->get_core(0);
 
+  die("handle_register_write");
+  /*
   if (n >= REG_XPR0 && n <= REG_XPR31) {
     p->state.XPR.write(n - REG_XPR0, value);
   } else if (n == REG_PC) {
@@ -511,6 +523,7 @@ void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet)
   } else {
     return send_packet("E07");
   }
+  */
 
   return send_packet("OK");
 }
@@ -574,7 +587,8 @@ void gdbserver_t::handle_continue(const std::vector<uint8_t> &packet)
   processor_t *p = sim->get_core(0);
   if (packet[2] != '#') {
     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
-    p->state.pc = consume_hex_number(iter, packet.end());
+    die("handle_continue");
+    // p->state.pc = consume_hex_number(iter, packet.end());
     if (*iter != '#')
       return send_packet("E30");
   }
@@ -589,7 +603,8 @@ void gdbserver_t::handle_step(const std::vector<uint8_t> &packet)
   processor_t *p = sim->get_core(0);
   if (packet[2] != '#') {
     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
-    p->state.pc = consume_hex_number(iter, packet.end());
+    die("handle_step");
+    //p->state.pc = consume_hex_number(iter, packet.end());
     if (*iter != '#')
       return send_packet("E40");
   }
@@ -662,6 +677,8 @@ void gdbserver_t::handle_breakpoint(const std::vector<uint8_t> &packet)
   }
 
   processor_t *p = sim->get_core(0);
+  die("handle_breakpoint");
+  /*
   mmu_t* mmu = p->mmu;
   if (insert) {
     bp.insert(mmu);
@@ -674,6 +691,7 @@ void gdbserver_t::handle_breakpoint(const std::vector<uint8_t> &packet)
   }
   mmu->flush_icache();
   sim->debug_mmu->flush_icache();
+  */
   return send_packet("OK");
 }
 
@@ -768,12 +786,13 @@ void gdbserver_t::handle()
   if (client_fd > 0) {
     processor_t *p = sim->get_core(0);
 
-    if (state == STATE_HALTING && sim->debug_module.get_interrupt(p->id) == 0) {
+    if (state == STATE_HALTING && sim->debug_module.get_interrupt(0) == 0) {
       // gdb requested a halt and now it's done.
       send_packet("T05");
       fprintf(stderr, "DPC: 0x%x\n", read_debug_ram(0));
       fprintf(stderr, "DCSR: 0x%x\n", read_debug_ram(2));
       state = STATE_HALTED;
+      p->debug = false;
     }
 
     /* TODO

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 3cb2f5a993f828e077923d65f7066c6c15444fbd..9b97120cc1886d3994bcc0de932c8cd6cc00c176 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -22,8 +22,8 @@
 #define STATE state
 
 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
-  : sim(sim), ext(NULL), disassembler(new disassembler_t),
-    id(id), run(false), debug(false)
+  : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
+    id(id), run(false)
 {
   parse_isa_string(isa);
 

diff --git a/riscv/processor.h b/riscv/processor.h
index 3511d303e351ab99c987abbe24400bc0bb481a76..9c2f7a66aa1da730fc72bcabeb54c983bbc1c831 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -122,6 +122,9 @@ public:
   bool load(reg_t addr, size_t len, uint8_t* bytes);
   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 
+  // When true, display disassembly of each instruction that's executed.
+  bool debug;
+
 private:
   sim_t* sim;
   mmu_t* mmu; // main memory is always accessed via the mmu
@@ -134,8 +137,6 @@ private:
   reg_t isa;
   std::string isa_string;
   bool run; // !reset
-  // When true, display disassembly of each instruction that's executed.
-  bool debug;
   bool histogram_enabled;
 
   std::vector<insn_desc_t> instructions;
@@ -155,7 +156,6 @@ private:
   friend class mmu_t;
   friend class rtc_t;
   friend class extension_t;
-  friend class gdbserver_t;
 
   void parse_isa_string(const char* isa);
   void build_opcode_map();