Merge branch 'display-patch' into libresoc-partsig

diff --cc nmigen/back/rtlil.py
Simple merge

diff --cc nmigen/hdl/ast.py
index 39fb33f4d7bd36b33936c5e9f3f962aed7532150,d2066750fcb897d5c80a0877ae0bd2bc63a2d120..1e0b5c799a5ae6b38f49987b475a6ebd50676fe7
--- 1/nmigen/hdl/ast.py
--- 2/nmigen/hdl/ast.py
+++ b/nmigen/hdl/ast.py
@@@ -1546,14 -1472,32 +1545,37 @@@ class Assume(Property)
  class Cover(Property):
      _kind = "cover"
  
+ @final
+ class Display(Statement):
+     _MustUse__warning = UnusedProperty
+ 
+     def __init__(self, text, *args):
+         super().__init__(src_loc_at=0)
+         self.text = text
+         self.args = args
+         self.test = Signal()
+         self._check = Signal(reset_less=True)
+         self._check.src_loc = self.src_loc
+         self._en = Signal(reset_less=True)
+         self._en.src_loc = self.src_loc
+ 
+     def _lhs_signals(self):
+         return SignalSet((self._en, self._check))
+ 
+     def _rhs_signals(self):
+         return self.test._rhs_signals()
+ 
+     def __repr__(self):
+         return "(display {!r})".format(self.text)
+ 
  
  # @final
 -class Switch(Statement):
 +def Switch(test, cases, *, src_loc=None, src_loc_at=0, case_src_locs={}):
 +    return test.__Switch__(cases, src_loc=src_loc, src_loc_at=src_loc_at,
 +                           case_src_locs=case_src_locs)
 +
 +
 +class _InternalSwitch(Statement):
      def __init__(self, test, cases, *, src_loc=None, src_loc_at=0, case_src_locs={}):
          if src_loc is None:
              super().__init__(src_loc_at=src_loc_at)

diff --cc nmigen/hdl/dsl.py
index bac2686aea8ea1b7567391902efb8e65bdd2192f,cf40c66aec61855033b3d8800078f4687351a2df..86e190e63f6fcfedce14fdb15b46d2373b2bed5e
--- 1/nmigen/hdl/dsl.py
--- 2/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@@ -493,7 -484,7 +493,7 @@@ class Module(_ModuleBuilderRoot, Elabor
              self._pop_ctrl()
  
          for stmt in Statement.cast(assigns):
-             if not compat_mode and not isinstance(stmt, (_InternalAssign, Assert, Assume, Cover)):
 -            if not compat_mode and not isinstance(stmt, (Assign, Assert, Assume, Cover, Display)):
++            if not compat_mode and not isinstance(stmt, (_InternalAssign, Assert, Assume, Cover, Display)):
                  raise SyntaxError(
                      "Only assignments and property checks may be appended to d.{}"
                      .format(domain_name(domain)))

diff --cc nmigen/hdl/xfrm.py
index c39e5234f3f29d8a3bf0487be1652eadfdde5c7b,4e043f77c01c7974acc62107360d2cad5eb44e82..94d8fbff9404209f0a3eff088d0c8dc35515ca93
--- 1/nmigen/hdl/xfrm.py
--- 2/nmigen/hdl/xfrm.py
+++ b/nmigen/hdl/xfrm.py
@@@ -213,7 -217,9 +217,9 @@@ class StatementVisitor(metaclass=ABCMet
              new_stmt = self.on_Assume(stmt)
          elif type(stmt) is Cover:
              new_stmt = self.on_Cover(stmt)
 -        elif isinstance(stmt, Switch):
+         elif type(stmt) is Display:
+             new_stmt = self.on_Display(stmt)
 +        elif isinstance(stmt, _InternalSwitch):
              # Uses `isinstance()` and not `type() is` because nmigen.compat requires it.
              new_stmt = self.on_Switch(stmt)
          elif isinstance(stmt, Iterable):