Added English language description for Negate instruction

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index 72b48bf3d32c0e09070c1526c9dee73da4f87dc9..fd90139713b74cb684b3a08e2eecadad7ff7ec14 100644 (file)
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -381,6 +381,23 @@ Pseudo-code:
 
     RT <- ¬(RA) + 1
 
+Description:
+
+       The sum ¬(RA) + 1 is placed into register RT.
+
+       If the processor is in 64-bit mode and register RA con-
+       tains the most negative 64-bit number (0x8000_
+       0000_0000_0000), the result is the most negative num-
+       ber and, if OE=1, OV is set to 1. If (RA) 32:63 contain the
+       most negative 32-bit number (0x8000_0000) and
+       OE=1, OV32 is set to 1.
+
+       Similarly, if the processor is in 32-bit mode and
+       (RA)32:63 contain the most negative 32-bit number
+       (0x8000_0000), the low-order 32 bits of the result con-
+       tain the most negative 32-bit number and, if OE=1, OV
+       and OV32 are set to 1.
+
 Special Registers Altered:
 
     CR0                     (if Rc=1)