ClockSignal as ClockSignal,
ResetSignal as ResetSignal)
from .hdl.cd import ClockDomain as ClockDomain
-from .hdl.ir import Fragment as Fragment, Instance as Instance
+from .hdl.ir import (Fragment as Fragment,
+ Instance as Instance,
+ Elaboratable as Elaboratable)
from .hdl.mem import Memory as Memory
from .hdl.rec import Record as Record
from .ast import Signal, Statement
from .cd import ClockDomain
# noinspection PyProtectedMember
-from .dsl import FSM
+from .dsl import FSM, Module
+from abc import ABCMeta, abstractmethod
-__all__ = ["Fragment", "Instance", "DriverConflict"]
+__all__ = ["Fragment", "Instance", "DriverConflict", "Elaboratable"]
+
+
+class Elaboratable(metaclass=ABCMeta):
+ @abstractmethod
+ def elaborate(self, platform: Any) -> Module:
+ ...
class DriverConflict(UserWarning):