From: Luke Kenneth Casson Leighton Date: Thu, 29 Nov 2018 00:25:17 +0000 (+0000) Subject: add Makefile for verilog compilation X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;ds=inline;p=rv32.git add Makefile for verilog compilation --- diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..85844f0 --- /dev/null +++ b/Makefile @@ -0,0 +1,6 @@ +rv32_sim: + iverilog -o rv32 -Wall cpu.v cpu_alu.v cpu_fetch_stage.v \ + cpu_memory_interface.v vga*.v cpu_decoder.v \ + block_memory.v block_memory_16kbit.v \ + main.v main_test.v +