From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 Jul 2020 12:09:14 +0000 (+0100)
Subject: add SR latch cxxrtl backend demo
X-Git-Tag: semi_working_ecp5~692
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;ds=sidebyside;h=17c1f0b98213a4b5660a48c9f8668d66c62f8110;p=soc.git

add SR latch cxxrtl backend demo
---

diff --git a/src/soc/experiment/sr/Makefile b/src/soc/experiment/sr/Makefile
new file mode 100644
index 00000000..72a8536a
--- /dev/null
+++ b/src/soc/experiment/sr/Makefile
@@ -0,0 +1,12 @@
+demo: build run
+
+build:
+	python3 sr.py >sr.il
+	yosys sr.il -o sr.cc
+	g++ `yosys-config --cxxflags` sr_driver.cc -o sr
+
+run:
+	./sr
+
+clean:
+	rm sr sr.d sr.il sr.cc
diff --git a/src/soc/experiment/sr/README.md b/src/soc/experiment/sr/README.md
new file mode 100644
index 00000000..83922855
--- /dev/null
+++ b/src/soc/experiment/sr/README.md
@@ -0,0 +1,5 @@
+# Demo of cxxrtl SR Latch
+
+shows how to compile a yosys "$sr" instance under the new cxxsim backend
+
+compile and run with "make demo"
diff --git a/src/soc/experiment/sr/sr.py b/src/soc/experiment/sr/sr.py
new file mode 100644
index 00000000..e55da210
--- /dev/null
+++ b/src/soc/experiment/sr/sr.py
@@ -0,0 +1,17 @@
+from nmigen import *
+from nmigen.back import rtlil
+
+
+sr_set = Signal(3)
+sr_clr = Signal(3)
+q = Signal(3)
+
+m = Module()
+m.submodules += Instance("$sr",
+    p_WIDTH=3,
+    p_SET_POLARITY=1,
+    p_CLR_POLARITY=1,
+	i_SET=sr_set,
+	i_CLR=sr_clr,
+	o_Q=q)
+print(rtlil.convert(m, ports=[sr_set, sr_clr, q]))
diff --git a/src/soc/experiment/sr/sr_driver.cc b/src/soc/experiment/sr/sr_driver.cc
new file mode 100644
index 00000000..5989c18a
--- /dev/null
+++ b/src/soc/experiment/sr/sr_driver.cc
@@ -0,0 +1,31 @@
+#include <stdio.h>
+
+#include "sr.cc"
+
+cxxrtl_design::p_top top;
+
+void step() {
+	top.step();
+	fprintf(stderr, "SET %d CLR %d Q %d\n",
+	        top.p_sr__set.data[0], top.p_sr__clr.data[0], top.p_q.data[0]);
+}
+
+int main() {
+	step();
+
+	top.p_sr__set = value<3>{3u};
+	step(); // set bits 0 & 1
+
+	top.p_sr__set = value<3>{0u};
+	top.p_sr__clr = value<3>{1u};
+	step(); // clear bit 0
+
+	top.p_sr__clr = value<3>{0u};
+	step(); // retain latched value
+
+	top.p_sr__set = value<3>{2u};
+	top.p_sr__clr = value<3>{2u};
+	step(); // clear bit 1, since CLR has priority over SET
+
+	return 0;
+}