From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 12 Nov 2018 07:06:22 +0000 (+0100)
Subject: plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5
X-Git-Tag: 24jan2021_ls180~1512
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;ds=sidebyside;h=425ad755ecfe713310b668fc4f26d110bb0b49bb;p=litex.git

plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5
---

diff --git a/litex/boards/platforms/versa.py b/litex/boards/platforms/versa.py
deleted file mode 100644
index ca9b6bd0..00000000
--- a/litex/boards/platforms/versa.py
+++ /dev/null
@@ -1,134 +0,0 @@
-# This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
-# License: BSD
-
-from litex.build.generic_platform import *
-from litex.build.lattice import LatticePlatform
-from litex.build.lattice.programmer import LatticeProgrammer
-
-
-_io = [
-    ("clk100", 0, Pins("L5"), IOStandard("LVDS25")),
-    ("rst_n", 0, Pins("A21"), IOStandard("LVCMOS33")),
-
-    ("user_led", 0, Pins("Y20"), IOStandard("LVCMOS33")),
-    ("user_led", 1, Pins("AA21"), IOStandard("LVCMOS33")),
-    ("user_led", 2, Pins("U18"), IOStandard("LVCMOS33")),
-    ("user_led", 3, Pins("U19"), IOStandard("LVCMOS33")),
-    ("user_led", 4, Pins("W19"), IOStandard("LVCMOS33")),
-    ("user_led", 5, Pins("V19"), IOStandard("LVCMOS33")),
-    ("user_led", 6, Pins("AB20"), IOStandard("LVCMOS33")),
-    ("user_led", 7, Pins("AA20"), IOStandard("LVCMOS33")),
-
-    ("user_dip_btn", 0, Pins("J7"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 1, Pins("J6"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 2, Pins("H2"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 3, Pins("H3"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 4, Pins("J3"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 5, Pins("K3"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 6, Pins("J2"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 7, Pins("J1"), IOStandard("LVCMOS15")),
-
-    ("serial", 0,
-        Subsignal("tx", Pins("B11"), IOStandard("LVCMOS33")),  # X4 IO0
-        Subsignal("rx", Pins("B12"), IOStandard("LVCMOS33")),  # X4 IO1
-    ),
-
-    ("eth_clocks", 0,
-        Subsignal("tx", Pins("C12")),
-        Subsignal("gtx", Pins("M2")),
-        Subsignal("rx", Pins("L4")),
-        IOStandard("LVCMOS33")
-    ),
-    ("eth", 0,
-        Subsignal("rst_n", Pins("L3")),
-        Subsignal("mdio", Pins("L2")),
-        Subsignal("mdc", Pins("V4")),
-        Subsignal("dv", Pins("M1")),
-        Subsignal("rx_er", Pins("M4")),
-        Subsignal("rx_data", Pins("M5 N1 N6 P6 T2 R2 P5 P3")),
-        Subsignal("tx_en", Pins("V3")),
-        Subsignal("tx_data", Pins("V1 U1 R3 P1 N5 N3 N4 N2")),
-        Subsignal("col", Pins("R1")),
-        Subsignal("crs", Pins("P4")),
-        IOStandard("LVCMOS33")
-    ),
-
-    ("eth_clocks", 1,
-        Subsignal("tx", Pins("M21")),
-        Subsignal("gtx", Pins("M19")),
-        Subsignal("rx", Pins("N19")),
-        IOStandard("LVCMOS33")
-    ),
-    ("eth", 1,
-        Subsignal("rst_n", Pins("R21")),
-        Subsignal("mdio", Pins("U16")),
-        Subsignal("mdc", Pins("Y18")),
-        Subsignal("dv", Pins("U15")),
-        Subsignal("rx_er", Pins("V20")),
-        Subsignal("rx_data", Pins("AB17 AA17 R19 V21 T17 R18 W21 Y21")),
-        Subsignal("tx_en", Pins("V22")),
-        Subsignal("tx_data", Pins("W22 R16 P17 Y22 T21 U22 P20 U20")),
-        Subsignal("col", Pins("N18")),
-        Subsignal("crs", Pins("P19")),
-        IOStandard("LVCMOS33")
-    ),
-]
-
-
-class Platform(LatticePlatform):
-    default_clk_name = "clk100"
-    default_clk_period = 10
-
-    def __init__(self):
-        LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
-
-    def do_finalize(self, fragment):
-        LatticePlatform.do_finalize(self, fragment)
-        try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
-        except ConstraintError:
-            pass
-        try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
-        except ConstraintError:
-            pass
-
-    def create_programmer(self):
-        _xcf_template = """
-<?xml version='1.0' encoding='utf-8' ?>
-<!DOCTYPE        ispXCF    SYSTEM    "IspXCF.dtd" >
-<ispXCF version="3.4.1">
-    <Comment></Comment>
-    <Chain>
-        <Comm>JTAG</Comm>
-        <Device>
-            <SelectedProg value="TRUE"/>
-            <Pos>1</Pos>
-            <Vendor>Lattice</Vendor>
-            <Family>LatticeECP3</Family>
-            <Name>LFE3-35EA</Name>
-            <File>{bitstream_file}</File>
-            <Operation>Fast Program</Operation>
-        </Device>
-    </Chain>
-    <ProjectOptions>
-        <Program>SEQUENTIAL</Program>
-        <Process>ENTIRED CHAIN</Process>
-        <OperationOverride>No Override</OperationOverride>
-        <StartTAP>TLR</StartTAP>
-        <EndTAP>TLR</EndTAP>
-        <VerifyUsercode value="FALSE"/>
-    </ProjectOptions>
-    <CableOptions>
-        <CableName>USB2</CableName>
-        <PortAdd>FTUSB-0</PortAdd>
-        <USBID>Dual RS232-HS A Location 0000 Serial A</USBID>
-        <JTAGPinSetting>
-            TRST    ABSENT;
-            ISPEN    ABSENT;
-        </JTAGPinSetting>
-    </CableOptions>
-</ispXCF>
-"""
-
-        return LatticeProgrammer(_xcf_template)
diff --git a/litex/boards/platforms/versa_ecp3.py b/litex/boards/platforms/versa_ecp3.py
new file mode 100644
index 00000000..ca9b6bd0
--- /dev/null
+++ b/litex/boards/platforms/versa_ecp3.py
@@ -0,0 +1,134 @@
+# This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+from litex.build.lattice.programmer import LatticeProgrammer
+
+
+_io = [
+    ("clk100", 0, Pins("L5"), IOStandard("LVDS25")),
+    ("rst_n", 0, Pins("A21"), IOStandard("LVCMOS33")),
+
+    ("user_led", 0, Pins("Y20"), IOStandard("LVCMOS33")),
+    ("user_led", 1, Pins("AA21"), IOStandard("LVCMOS33")),
+    ("user_led", 2, Pins("U18"), IOStandard("LVCMOS33")),
+    ("user_led", 3, Pins("U19"), IOStandard("LVCMOS33")),
+    ("user_led", 4, Pins("W19"), IOStandard("LVCMOS33")),
+    ("user_led", 5, Pins("V19"), IOStandard("LVCMOS33")),
+    ("user_led", 6, Pins("AB20"), IOStandard("LVCMOS33")),
+    ("user_led", 7, Pins("AA20"), IOStandard("LVCMOS33")),
+
+    ("user_dip_btn", 0, Pins("J7"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 1, Pins("J6"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 2, Pins("H2"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 3, Pins("H3"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 4, Pins("J3"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 5, Pins("K3"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 6, Pins("J2"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 7, Pins("J1"), IOStandard("LVCMOS15")),
+
+    ("serial", 0,
+        Subsignal("tx", Pins("B11"), IOStandard("LVCMOS33")),  # X4 IO0
+        Subsignal("rx", Pins("B12"), IOStandard("LVCMOS33")),  # X4 IO1
+    ),
+
+    ("eth_clocks", 0,
+        Subsignal("tx", Pins("C12")),
+        Subsignal("gtx", Pins("M2")),
+        Subsignal("rx", Pins("L4")),
+        IOStandard("LVCMOS33")
+    ),
+    ("eth", 0,
+        Subsignal("rst_n", Pins("L3")),
+        Subsignal("mdio", Pins("L2")),
+        Subsignal("mdc", Pins("V4")),
+        Subsignal("dv", Pins("M1")),
+        Subsignal("rx_er", Pins("M4")),
+        Subsignal("rx_data", Pins("M5 N1 N6 P6 T2 R2 P5 P3")),
+        Subsignal("tx_en", Pins("V3")),
+        Subsignal("tx_data", Pins("V1 U1 R3 P1 N5 N3 N4 N2")),
+        Subsignal("col", Pins("R1")),
+        Subsignal("crs", Pins("P4")),
+        IOStandard("LVCMOS33")
+    ),
+
+    ("eth_clocks", 1,
+        Subsignal("tx", Pins("M21")),
+        Subsignal("gtx", Pins("M19")),
+        Subsignal("rx", Pins("N19")),
+        IOStandard("LVCMOS33")
+    ),
+    ("eth", 1,
+        Subsignal("rst_n", Pins("R21")),
+        Subsignal("mdio", Pins("U16")),
+        Subsignal("mdc", Pins("Y18")),
+        Subsignal("dv", Pins("U15")),
+        Subsignal("rx_er", Pins("V20")),
+        Subsignal("rx_data", Pins("AB17 AA17 R19 V21 T17 R18 W21 Y21")),
+        Subsignal("tx_en", Pins("V22")),
+        Subsignal("tx_data", Pins("W22 R16 P17 Y22 T21 U22 P20 U20")),
+        Subsignal("col", Pins("N18")),
+        Subsignal("crs", Pins("P19")),
+        IOStandard("LVCMOS33")
+    ),
+]
+
+
+class Platform(LatticePlatform):
+    default_clk_name = "clk100"
+    default_clk_period = 10
+
+    def __init__(self):
+        LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        try:
+            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
+        except ConstraintError:
+            pass
+        try:
+            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
+        except ConstraintError:
+            pass
+
+    def create_programmer(self):
+        _xcf_template = """
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE        ispXCF    SYSTEM    "IspXCF.dtd" >
+<ispXCF version="3.4.1">
+    <Comment></Comment>
+    <Chain>
+        <Comm>JTAG</Comm>
+        <Device>
+            <SelectedProg value="TRUE"/>
+            <Pos>1</Pos>
+            <Vendor>Lattice</Vendor>
+            <Family>LatticeECP3</Family>
+            <Name>LFE3-35EA</Name>
+            <File>{bitstream_file}</File>
+            <Operation>Fast Program</Operation>
+        </Device>
+    </Chain>
+    <ProjectOptions>
+        <Program>SEQUENTIAL</Program>
+        <Process>ENTIRED CHAIN</Process>
+        <OperationOverride>No Override</OperationOverride>
+        <StartTAP>TLR</StartTAP>
+        <EndTAP>TLR</EndTAP>
+        <VerifyUsercode value="FALSE"/>
+    </ProjectOptions>
+    <CableOptions>
+        <CableName>USB2</CableName>
+        <PortAdd>FTUSB-0</PortAdd>
+        <USBID>Dual RS232-HS A Location 0000 Serial A</USBID>
+        <JTAGPinSetting>
+            TRST    ABSENT;
+            ISPEN    ABSENT;
+        </JTAGPinSetting>
+    </CableOptions>
+</ispXCF>
+"""
+
+        return LatticeProgrammer(_xcf_template)
diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py
new file mode 100644
index 00000000..8ecb2633
--- /dev/null
+++ b/litex/boards/platforms/versa_ecp5.py
@@ -0,0 +1,139 @@
+# This file is Copyright (c) 2017 Serge 'q3k' Bazanski <serge@bazanski.pl>
+# License: BSD
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+from litex.build.lattice.programmer import LatticeProgrammer
+
+
+_io = [
+    ("clk100", 0, Pins("P3"), IOStandard("LVDS")),
+    ("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")),
+
+    ("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")),
+    ("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")),
+    ("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")),
+    ("user_led", 3, Pins("E18"), IOStandard("LVCMOS25")),
+    ("user_led", 4, Pins("F17"), IOStandard("LVCMOS25")),
+    ("user_led", 5, Pins("F18"), IOStandard("LVCMOS25")),
+    ("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")),
+    ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
+
+    ("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")),
+    ("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")),
+    ("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")),
+    ("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")),
+    ("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
+
+    ("serial", 0,
+        Subsignal("rx", Pins("C11"), IOStandard("LVCMOS33")),
+        Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
+    ),
+
+
+    ("eth_clocks", 0,
+        Subsignal("tx", Pins("P19")),
+        Subsignal("rx", Pins("L20")),
+        IOStandard("LVCMOS25")
+    ),
+    ("eth", 0,
+        Subsignal("rst_n", Pins("U17")),
+        Subsignal("mdio", Pins("U18")),
+        Subsignal("mdc", Pins("T18")),
+        Subsignal("rx_ctl", Pins("U19")),
+        Subsignal("rx_data", Pins("T20 U20 T19 R18")),
+        Subsignal("tx_ctl", Pins("R20")),
+        Subsignal("tx_data", Pins("N19 N20 P18 P20")),
+        IOStandard("LVCMOS25")
+    ),
+
+    ("eth_clocks", 1,
+        Subsignal("tx", Pins("C20")),
+        Subsignal("rx", Pins("J19")),
+        IOStandard("LVCMOS25")
+    ),
+    ("eth", 1,
+        Subsignal("rst_n", Pins("F20")),
+        Subsignal("mdio", Pins("H20")),
+        Subsignal("mdc", Pins("G19")),
+        Subsignal("rx_ctl", Pins("F19")),
+        Subsignal("rx_data", Pins("G18 G16 H18 H17")),
+        Subsignal("tx_ctl", Pins("E19")),
+        Subsignal("tx_data", Pins("J17 J16 D19 D20")),
+        IOStandard("LVCMOS25")
+    ),
+]
+
+
+class Platform(LatticePlatform):
+    default_clk_name = "clk100"
+    default_clk_period = 10
+
+    def __init__(self, **kwargs):
+        LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, **kwargs)
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        try:
+            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
+        except ConstraintError:
+            pass
+        try:
+            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
+        except ConstraintError:
+            pass
+
+    def create_programmer(self):
+        _xcf_template = """
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE        ispXCF    SYSTEM    "IspXCF.dtd" >
+<ispXCF version="3.4.1">
+    <Comment></Comment>
+    <Chain>
+        <Comm>JTAG</Comm>
+        <Device>
+            <SelectedProg value="TRUE"/>
+            <Pos>1</Pos>
+            <Vendor>Lattice</Vendor>
+            <Family>ECP5UM5G</Family>
+            <Name>LFE5UM5G-45F</Name>
+            <IDCode>0x81112043</IDCode>
+            <File>{bitstream_file}</File>
+            <Operation>Fast Program</Operation>
+        </Device>
+        <Device>
+            <SelectedProg value="FALSE"/>
+            <Pos>2</Pos>
+            <Vendor>Lattice</Vendor>
+            <Family>ispCLOCK</Family>
+            <Name>ispPAC-CLK5406D</Name>
+            <IDCode>0x00191043</IDCode>
+            <Operation>Erase,Program,Verify</Operation>
+            <Bypass>
+                <InstrLen>8</InstrLen>
+                <InstrVal>11111111</InstrVal>
+                <BScanLen>1</BScanLen>
+                <BScanVal>0</BScanVal>
+            </Bypass>
+        </Device>
+    </Chain>
+    <ProjectOptions>
+        <Program>SEQUENTIAL</Program>
+        <Process>ENTIRED CHAIN</Process>
+        <OperationOverride>No Override</OperationOverride>
+        <StartTAP>TLR</StartTAP>
+        <EndTAP>TLR</EndTAP>
+        <VerifyUsercode value="FALSE"/>
+    </ProjectOptions>
+    <CableOptions>
+        <CableName>USB2</CableName>
+        <PortAdd>FTUSB-0</PortAdd>
+        <USBID>LATTICE ECP5_5G VERSA BOARD A Location 0000 Serial Lattice ECP5_5G VERSA Board A</USBID>
+    </CableOptions>
+</ispXCF>
+"""
+
+        return LatticeProgrammer(_xcf_template)
diff --git a/litex/boards/platforms/versaecp55g.py b/litex/boards/platforms/versaecp55g.py
deleted file mode 100644
index 8ecb2633..00000000
--- a/litex/boards/platforms/versaecp55g.py
+++ /dev/null
@@ -1,139 +0,0 @@
-# This file is Copyright (c) 2017 Serge 'q3k' Bazanski <serge@bazanski.pl>
-# License: BSD
-
-from litex.build.generic_platform import *
-from litex.build.lattice import LatticePlatform
-from litex.build.lattice.programmer import LatticeProgrammer
-
-
-_io = [
-    ("clk100", 0, Pins("P3"), IOStandard("LVDS")),
-    ("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")),
-
-    ("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")),
-    ("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")),
-    ("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")),
-    ("user_led", 3, Pins("E18"), IOStandard("LVCMOS25")),
-    ("user_led", 4, Pins("F17"), IOStandard("LVCMOS25")),
-    ("user_led", 5, Pins("F18"), IOStandard("LVCMOS25")),
-    ("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")),
-    ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
-
-    ("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")),
-    ("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")),
-    ("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")),
-    ("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")),
-    ("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
-
-    ("serial", 0,
-        Subsignal("rx", Pins("C11"), IOStandard("LVCMOS33")),
-        Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
-    ),
-
-
-    ("eth_clocks", 0,
-        Subsignal("tx", Pins("P19")),
-        Subsignal("rx", Pins("L20")),
-        IOStandard("LVCMOS25")
-    ),
-    ("eth", 0,
-        Subsignal("rst_n", Pins("U17")),
-        Subsignal("mdio", Pins("U18")),
-        Subsignal("mdc", Pins("T18")),
-        Subsignal("rx_ctl", Pins("U19")),
-        Subsignal("rx_data", Pins("T20 U20 T19 R18")),
-        Subsignal("tx_ctl", Pins("R20")),
-        Subsignal("tx_data", Pins("N19 N20 P18 P20")),
-        IOStandard("LVCMOS25")
-    ),
-
-    ("eth_clocks", 1,
-        Subsignal("tx", Pins("C20")),
-        Subsignal("rx", Pins("J19")),
-        IOStandard("LVCMOS25")
-    ),
-    ("eth", 1,
-        Subsignal("rst_n", Pins("F20")),
-        Subsignal("mdio", Pins("H20")),
-        Subsignal("mdc", Pins("G19")),
-        Subsignal("rx_ctl", Pins("F19")),
-        Subsignal("rx_data", Pins("G18 G16 H18 H17")),
-        Subsignal("tx_ctl", Pins("E19")),
-        Subsignal("tx_data", Pins("J17 J16 D19 D20")),
-        IOStandard("LVCMOS25")
-    ),
-]
-
-
-class Platform(LatticePlatform):
-    default_clk_name = "clk100"
-    default_clk_period = 10
-
-    def __init__(self, **kwargs):
-        LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, **kwargs)
-
-    def do_finalize(self, fragment):
-        LatticePlatform.do_finalize(self, fragment)
-        try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
-        except ConstraintError:
-            pass
-        try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
-        except ConstraintError:
-            pass
-
-    def create_programmer(self):
-        _xcf_template = """
-<?xml version='1.0' encoding='utf-8' ?>
-<!DOCTYPE        ispXCF    SYSTEM    "IspXCF.dtd" >
-<ispXCF version="3.4.1">
-    <Comment></Comment>
-    <Chain>
-        <Comm>JTAG</Comm>
-        <Device>
-            <SelectedProg value="TRUE"/>
-            <Pos>1</Pos>
-            <Vendor>Lattice</Vendor>
-            <Family>ECP5UM5G</Family>
-            <Name>LFE5UM5G-45F</Name>
-            <IDCode>0x81112043</IDCode>
-            <File>{bitstream_file}</File>
-            <Operation>Fast Program</Operation>
-        </Device>
-        <Device>
-            <SelectedProg value="FALSE"/>
-            <Pos>2</Pos>
-            <Vendor>Lattice</Vendor>
-            <Family>ispCLOCK</Family>
-            <Name>ispPAC-CLK5406D</Name>
-            <IDCode>0x00191043</IDCode>
-            <Operation>Erase,Program,Verify</Operation>
-            <Bypass>
-                <InstrLen>8</InstrLen>
-                <InstrVal>11111111</InstrVal>
-                <BScanLen>1</BScanLen>
-                <BScanVal>0</BScanVal>
-            </Bypass>
-        </Device>
-    </Chain>
-    <ProjectOptions>
-        <Program>SEQUENTIAL</Program>
-        <Process>ENTIRED CHAIN</Process>
-        <OperationOverride>No Override</OperationOverride>
-        <StartTAP>TLR</StartTAP>
-        <EndTAP>TLR</EndTAP>
-        <VerifyUsercode value="FALSE"/>
-    </ProjectOptions>
-    <CableOptions>
-        <CableName>USB2</CableName>
-        <PortAdd>FTUSB-0</PortAdd>
-        <USBID>LATTICE ECP5_5G VERSA BOARD A Location 0000 Serial Lattice ECP5_5G VERSA Board A</USBID>
-    </CableOptions>
-</ispXCF>
-"""
-
-        return LatticeProgrammer(_xcf_template)