From: Luke Kenneth Casson Leighton Date: Tue, 11 Aug 2020 13:13:13 +0000 (+0100) Subject: reduce regfile ports by creating separate STATE regfile X-Git-Tag: semi_working_ecp5~402 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;ds=sidebyside;h=847b84d7e0a1fb8c86512cd85a19844fe066daea;p=soc.git reduce regfile ports by creating separate STATE regfile --- diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py index 7413cdd6..1dd3f0e4 100644 --- a/src/soc/decoder/power_regspec_map.py +++ b/src/soc/decoder/power_regspec_map.py @@ -35,7 +35,7 @@ has to be "remapped" to internal SPR Enum indices (see SPRMap in PowerDecode2) see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs """ from nmigen import Const -from soc.regfile.regfiles import XERRegs, FastRegs +from soc.regfile.regfiles import XERRegs, FastRegs, StateRegs from soc.decoder.power_enums import CryIn @@ -82,22 +82,26 @@ def regspec_decode_read(e, regfile, name): if name == 'xer_ca': return (e.do.input_carry == CryIn.CA.value) | e.xer_in, CA + # STATE regfile + + if regfile == 'STATE': + # STATE register numbering is *unary* encoded + PC = 1<