From: Christoph Bumiller <e0425955@student.tuwien.ac.at>
Date: Sat, 15 Aug 2009 14:22:27 +0000 (+0200)
Subject: nv50: align registers used with TEX to 4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;ds=sidebyside;h=a2af40b846e0b510887aaf15c2777387a3caae62;p=mesa.git

nv50: align registers used with TEX to 4

The TEX instruction is passed the first index of a contiguous
range of 4 TEMP registers that contain coordinates / LOD and,
after execution, the texel values.
It seems the first index is required to be a multiple of 4 on
some (older ?) cards.
---

diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index fefccd0b2a8..e45769c0692 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -251,7 +251,7 @@ alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
 
 	if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
 	    pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
-		return alloc_temp4(pc, dst, idx + 1);
+		return alloc_temp4(pc, dst, idx + 4);
 
 	for (i = 0; i < 4; i++) {
 		dst[i] = CALLOC_STRUCT(nv50_reg);
@@ -1014,6 +1014,7 @@ emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
 		break;
 	}
 
+	/* some cards need t[0]'s hw index to be a multiple of 4 */
 	alloc_temp4(pc, t, 0);
 
 	if (proj) {