From: Howard Mao Date: Wed, 22 Jun 2016 22:37:33 +0000 (-0700) Subject: split up rv64uf and rv64ud isa tests X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;ds=sidebyside;h=b6b5e81217c1f2a70ecb6883b1756859cd7bb999;p=riscv-tests.git split up rv64uf and rv64ud isa tests --- diff --git a/isa/Makefile b/isa/Makefile index 636cbbe..d07dfa6 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -6,6 +6,7 @@ src_dir := . include $(src_dir)/rv64ui/Makefrag include $(src_dir)/rv64uf/Makefrag +include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64mi/Makefrag include $(src_dir)/rv32ui/Makefrag @@ -66,6 +67,7 @@ $(eval $(call compile_template,rv32mi,-m32)) ifeq ($(XLEN),64) $(eval $(call compile_template,rv64ui)) $(eval $(call compile_template,rv64uf)) +$(eval $(call compile_template,rv64ud)) $(eval $(call compile_template,rv64si)) $(eval $(call compile_template,rv64mi)) endif diff --git a/isa/rv64ud/Makefrag b/isa/rv64ud/Makefrag new file mode 100644 index 0000000..6e8be9c --- /dev/null +++ b/isa/rv64ud/Makefrag @@ -0,0 +1,12 @@ +#======================================================================= +# Makefrag for rv64ud tests +#----------------------------------------------------------------------- + +rv64ud_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin fsgnj \ + ldst move structural recoding \ + +rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests)) +rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests)) + +spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests) diff --git a/isa/rv64ud/fadd.S b/isa/rv64ud/fadd.S new file mode 100644 index 0000000..4a314da --- /dev/null +++ b/isa/rv64ud/fadd.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fadd.S +#----------------------------------------------------------------------------- +# +# Test f{add|sub|mul}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fadd.d, 0, 3.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 3, fadd.d, 1, -1234, -1235.1, 1.1 ); + TEST_FP_OP2_D( 4, fadd.d, 1, 3.14159266, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_D( 5, fsub.d, 0, 1.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 6, fsub.d, 1, -1234, -1235.1, -1.1 ); + TEST_FP_OP2_D( 7, fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_D( 8, fmul.d, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 9, fmul.d, 1, 1358.61, -1235.1, -1.1 ); + TEST_FP_OP2_D(10, fmul.d, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); + + # Is the canonical NaN generated for Inf - Inf? + TEST_FP_OP2_D(11, fsub.d, 0x10, 0d:7ff8000000000000, Inf, Inf); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fclass.S b/isa/rv64ud/fclass.S new file mode 100644 index 0000000..3daace0 --- /dev/null +++ b/isa/rv64ud/fclass.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fclass.S +#----------------------------------------------------------------------------- +# +# Test fclass.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + #define TEST_FCLASS_D(testnum, correct, input) \ + TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ + fclass.d a0, fa0) + + TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 ) + TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 ) + TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff ) + TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 ) + TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 ) + TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff ) + TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 ) + TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 ) + TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 ) + TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fcmp.S b/isa/rv64ud/fcmp.S new file mode 100644 index 0000000..173dc88 --- /dev/null +++ b/isa/rv64ud/fcmp.S @@ -0,0 +1,37 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcmp.S +#----------------------------------------------------------------------------- +# +# Test f{eq|lt|le}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_CMP_OP_D( 2, feq.d, 1, -1.36, -1.36) + TEST_FP_CMP_OP_D( 3, fle.d, 1, -1.36, -1.36) + TEST_FP_CMP_OP_D( 4, flt.d, 0, -1.36, -1.36) + + TEST_FP_CMP_OP_D( 5, feq.d, 0, -1.37, -1.36) + TEST_FP_CMP_OP_D( 6, fle.d, 1, -1.37, -1.36) + TEST_FP_CMP_OP_D( 7, flt.d, 1, -1.37, -1.36) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fcvt.S b/isa/rv64ud/fcvt.S new file mode 100644 index 0000000..4f25d07 --- /dev/null +++ b/isa/rv64ud/fcvt.S @@ -0,0 +1,56 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt.S +#----------------------------------------------------------------------------- +# +# Test fcvt.d.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_INT_FP_OP_D(2, fcvt.d.w, 2.0, 2); + TEST_INT_FP_OP_D(3, fcvt.d.w, -2.0, -2); + + TEST_INT_FP_OP_D(4, fcvt.d.wu, 2.0, 2); + TEST_INT_FP_OP_D(5, fcvt.d.wu, 4294967294, -2); + + TEST_INT_FP_OP_D(6, fcvt.d.l, 2.0, 2); + TEST_INT_FP_OP_D(7, fcvt.d.l, -2.0, -2); + + TEST_INT_FP_OP_D(8, fcvt.d.lu, 2.0, 2); + TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2); + + TEST_FCVT_S_D(10, -1.5, -1.5) + TEST_FCVT_D_S(11, -1.5, -1.5) + + TEST_CASE(12, a0, 0x7ff8000000000000, + la a1, test_data_22; + ld a2, 0(a1); + fmv.d.x f2, a2; + fcvt.s.d f2, f2; + fcvt.d.s f2, f2; + fmv.x.d a0, f2; + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +test_data_22: + .dword 0x7ffcffffffff8004 + +RVTEST_DATA_END diff --git a/isa/rv64ud/fcvt_w.S b/isa/rv64ud/fcvt_w.S new file mode 100644 index 0000000..50e794c --- /dev/null +++ b/isa/rv64ud/fcvt_w.S @@ -0,0 +1,102 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt_w.S +#----------------------------------------------------------------------------- +# +# Test fcvt{wu|w|lu|l}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_INT_OP_D( 2, fcvt.w.d, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_D( 3, fcvt.w.d, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_D( 4, fcvt.w.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D( 5, fcvt.w.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D( 6, fcvt.w.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D( 7, fcvt.w.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D( 8, fcvt.w.d, 0x10, -1<<31, -3e9, rtz); + TEST_FP_INT_OP_D( 9, fcvt.w.d, 0x10, (1<<31)-1, 3e9, rtz); + + TEST_FP_INT_OP_D(12, fcvt.wu.d, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_D(13, fcvt.wu.d, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_D(14, fcvt.wu.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(15, fcvt.wu.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(16, fcvt.wu.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(17, fcvt.wu.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz); + + TEST_FP_INT_OP_D(22, fcvt.l.d, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_D(23, fcvt.l.d, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_D(24, fcvt.l.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(25, fcvt.l.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(26, fcvt.l.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(27, fcvt.l.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(28, fcvt.l.d, 0x00,-3000000000, -3e9, rtz); + TEST_FP_INT_OP_D(29, fcvt.l.d, 0x00, 3000000000, 3e9, rtz); + TEST_FP_INT_OP_D(20, fcvt.l.d, 0x10, -1<<63,-3e19, rtz); + TEST_FP_INT_OP_D(21, fcvt.l.d, 0x10, (1<<63)-1, 3e19, rtz); + + TEST_FP_INT_OP_D(32, fcvt.lu.d, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_D(33, fcvt.lu.d, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_D(34, fcvt.lu.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(35, fcvt.lu.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(36, fcvt.lu.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz); + + # test negative NaN, negative infinity conversion + TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1) + TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1) + TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1) + TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1) + + # test positive NaN, positive infinity conversion + TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1) + TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1) + TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1) + TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1) + + # test NaN, infinity conversions to unsigned integer + TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1) + TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1) + TEST_CASE(64, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1) + TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1) + TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1) + TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1) + TEST_CASE(68, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1) + TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +# -NaN, NaN, -inf, +inf +tdat: +.word 0xffffffff +.word 0x7fffffff +.word 0xff800000 +.word 0x7f800000 + +tdat_d: +.dword 0xffffffffffffffff +.dword 0x7fffffffffffffff +.dword 0xfff0000000000000 +.dword 0x7ff0000000000000 + +RVTEST_DATA_END diff --git a/isa/rv64ud/fdiv.S b/isa/rv64ud/fdiv.S new file mode 100644 index 0000000..8a9fd4d --- /dev/null +++ b/isa/rv64ud/fdiv.S @@ -0,0 +1,42 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fdiv.S +#----------------------------------------------------------------------------- +# +# Test f{div|sqrt}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_D( 3, fdiv.d, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_D( 4, fdiv.d, 0, 3.14159265, 3.14159265, 1.0 ); + + TEST_FP_OP1_D( 5, fsqrt.d, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_D( 6, fsqrt.d, 0, 100, 10000 ); + + TEST_FP_OP1_D_DWORD_RESULT(16, fsqrt.d, 0x10, 0x7FF8000000000000, -1.0 ); + + TEST_FP_OP1_D( 7, fsqrt.d, 1, 13.076696830622021, 171.0); + + TEST_FP_OP1_D( 8, fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fmadd.S b/isa/rv64ud/fmadd.S new file mode 100644 index 0000000..7a69aad --- /dev/null +++ b/isa/rv64ud/fmadd.S @@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmadd.S +#----------------------------------------------------------------------------- +# +# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP3_D( 2, fmadd.d, 0, 3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 3, fmadd.d, 1, 1236.1999999999999, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D( 4, fmadd.d, 0, -12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D( 5, fnmadd.d, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 6, fnmadd.d, 1, -1236.1999999999999, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D( 7, fnmadd.d, 0, 12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D( 8, fmsub.d, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 9, fmsub.d, 1, 1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D(10, fmsub.d, 0, -8.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D(11, fnmsub.d, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D(12, fnmsub.d, 1, -1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D(13, fnmsub.d, 0, 8.0, 2.0, -5.0, -2.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fmin.S b/isa/rv64ud/fmin.S new file mode 100644 index 0000000..82641bc --- /dev/null +++ b/isa/rv64ud/fmin.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmin.S +#----------------------------------------------------------------------------- +# +# Test f{min|max}.d instructinos. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fmin.d, 0, 1.0, 2.5, 1.0 ); + TEST_FP_OP2_D( 3, fmin.d, 0, -1235.1, -1235.1, 1.1 ); + TEST_FP_OP2_D( 4, fmin.d, 0, -1235.1, 1.1, -1235.1 ); + TEST_FP_OP2_D( 5, fmin.d, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_D( 6, fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 ); + TEST_FP_OP2_D( 7, fmin.d, 0, -2.0, -1.0, -2.0 ); + + TEST_FP_OP2_D(12, fmax.d, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_D(13, fmax.d, 0, 1.1, -1235.1, 1.1 ); + TEST_FP_OP2_D(14, fmax.d, 0, 1.1, 1.1, -1235.1 ); + TEST_FP_OP2_D(15, fmax.d, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_D(16, fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 ); + TEST_FP_OP2_D(17, fmax.d, 0, -1.0, -1.0, -2.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fsgnj.S b/isa/rv64ud/fsgnj.S new file mode 100644 index 0000000..e914777 --- /dev/null +++ b/isa/rv64ud/fsgnj.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fsgnj.S +#----------------------------------------------------------------------------- +# +# Test fsgn{j|jn|x}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fsgnj.d, 0, -6.3, 6.3, -1.0 ); + TEST_FP_OP2_D( 3, fsgnj.d, 0, 7.3, 7.3, 2.0 ); + TEST_FP_OP2_D( 4, fsgnj.d, 0, -8.3, -8.3, -3.0 ); + TEST_FP_OP2_D( 5, fsgnj.d, 0, 9.3, -9.3, 4.0 ); + + TEST_FP_OP2_D(12, fsgnjn.d, 0, 6.3, 6.3, -1.0 ); + TEST_FP_OP2_D(13, fsgnjn.d, 0, -7.3, 7.3, 2.0 ); + TEST_FP_OP2_D(14, fsgnjn.d, 0, 8.3, -8.3, -3.0 ); + TEST_FP_OP2_D(15, fsgnjn.d, 0, -9.3, -9.3, 4.0 ); + + TEST_FP_OP2_D(22, fsgnjx.d, 0, -6.3, 6.3, -1.0 ); + TEST_FP_OP2_D(23, fsgnjx.d, 0, 7.3, 7.3, 2.0 ); + TEST_FP_OP2_D(24, fsgnjx.d, 0, 8.3, -8.3, -3.0 ); + TEST_FP_OP2_D(25, fsgnjx.d, 0, -9.3, -9.3, 4.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/ldst.S b/isa/rv64ud/ldst.S new file mode 100644 index 0000000..59084e3 --- /dev/null +++ b/isa/rv64ud/ldst.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + TEST_CASE(2, a0, 0x40000000bf800000, la a1, tdat; fld f2, 0(a1); fsd f2, 16(a1); ld a0, 16(a1)) + TEST_CASE(3, a0, 0xc080000040400000, la a1, tdat; fld f2, 8(a1); fsd f2, 16(a1); ld a0, 16(a1)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END diff --git a/isa/rv64ud/move.S b/isa/rv64ud/move.S new file mode 100644 index 0000000..806d4de --- /dev/null +++ b/isa/rv64ud/move.S @@ -0,0 +1,36 @@ +# See LICENSE for license details. + +#***************************************************************************** +# move.S +#----------------------------------------------------------------------------- +# +# This test verifies that mxtf.[s,d], mftx.[s,d], fssr, frsr, +# and fsgnj[x|n].d work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +li a0, 1 +fssr a0 + + TEST_CASE(2, a1, 1, li a0, 0x1234; fssr a1, a0) + TEST_CASE(3, a0, 0x34, frsr a0) + TEST_CASE(4, a0, 0x34, frsr a0) + + TEST_CASE(5, a0, 0x3FF02468A0000000, li a1, 0x3FF02468A0000000; fmv.d.x f1, a1; fmv.x.d a0, f1) + TEST_CASE(6, a0, 0xBFF02468A0001000, li a1, 0x3FF02468A0001000; li a2, -1; fmv.d.x f1, a1; fmv.d.x f2, a2; fsgnj.d f0, f1, f2; fmv.x.d a0, f0) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/recoding.S b/isa/rv64ud/recoding.S new file mode 100644 index 0000000..69ad665 --- /dev/null +++ b/isa/rv64ud/recoding.S @@ -0,0 +1,67 @@ +# See LICENSE for license details. + +#***************************************************************************** +# recoding.S +#----------------------------------------------------------------------------- +# +# Test corner cases of John Hauser's microarchitectural recoding scheme. +# There are twice as many recoded values as IEEE-754 values; some of these +# extras are redundant (e.g. Inf) and others are illegal (subnormals with +# too many bits set). +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + # Make sure infinities with different mantissas compare as equal. + fld f0, minf, a0 + fld f1, three, a0 + fmul.d f1, f1, f0 + TEST_CASE( 2, a0, 1, feq.d a0, f0, f1) + TEST_CASE( 3, a0, 1, fle.d a0, f0, f1) + TEST_CASE( 4, a0, 0, flt.d a0, f0, f1) + + # Likewise, but for zeroes. + fcvt.d.w f0, x0 + li a0, 1 + fcvt.d.w f1, a0 + fmul.d f1, f1, f0 + TEST_CASE(5, a0, 1, feq.d a0, f0, f1) + TEST_CASE(6, a0, 1, fle.d a0, f0, f1) + TEST_CASE(7, a0, 0, flt.d a0, f0, f1) + + # When converting small doubles to single-precision subnormals, + # ensure that the extra precision is discarded. + flw f0, big, a0 + fld f1, tiny, a0 + fcvt.s.d f1, f1 + fmul.s f0, f0, f1 + fmv.x.s a0, f0 + lw a1, small + TEST_CASE(10, a0, 0, sub a0, a0, a1) + + # Make sure FSD+FLD correctly saves and restores a single-precision value. + flw f0, three, a0 + fadd.s f1, f0, f0 + fadd.s f0, f0, f0 + fsd f0, tiny, a0 + fld f0, tiny, a0 + TEST_CASE(20, a0, 1, feq.s a0, f0, f1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +minf: .double -Inf +three: .double 3.0 +big: .float 1221 +small: .float 2.9133121e-37 +tiny: .double 2.3860049081905093e-40 + +RVTEST_DATA_END diff --git a/isa/rv64ud/structural.S b/isa/rv64ud/structural.S new file mode 100644 index 0000000..76c6691 --- /dev/null +++ b/isa/rv64ud/structural.S @@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# structural.S +#----------------------------------------------------------------------------- +# +# This test verifies that the FPU correctly obviates structural hazards on its +# writeback port (e.g. fadd followed by fsgnj) +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +li x25, 1 + +li x2, 0x3FF0000000000000 +li x1, 0x3F800000 + +#define TEST(nops, errcode) \ + fmv.d.x f4, x0 ;\ + fmv.s.x f3, x0 ;\ + fmv.d.x f2, x2 ;\ + fmv.s.x f1, x1 ;\ + j 1f ;\ + .align 5 ;\ +1:fmul.d f4, f2, f2 ;\ + nops ;\ + fsgnj.s f3, f1, f1 ;\ + fmv.x.d x4, f4 ;\ + fmv.x.s x3, f3 ;\ + beq x1, x3, 2f ;\ + RVTEST_FAIL ;\ +2:beq x2, x4, 2f ;\ + RVTEST_FAIL; \ +2:fmv.d.x f2, zero ;\ + fmv.s.x f1, zero ;\ + +TEST(;,2) +TEST(nop,4) +TEST(nop;nop,6) +TEST(nop;nop;nop,8) +TEST(nop;nop;nop;nop,10) +TEST(nop;nop;nop;nop;nop,12) +TEST(nop;nop;nop;nop;nop;nop,14) + +RVTEST_PASS + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uf/Makefrag b/isa/rv64uf/Makefrag index 978084a..d3c3f23 100644 --- a/isa/rv64uf/Makefrag +++ b/isa/rv64uf/Makefrag @@ -4,7 +4,7 @@ rv64uf_sc_tests = \ fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin fsgnj \ - ldst move structural recoding \ + ldst move recoding \ rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests)) rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests)) diff --git a/isa/rv64uf/fadd.S b/isa/rv64uf/fadd.S index a5f3e42..800dc8c 100644 --- a/isa/rv64uf/fadd.S +++ b/isa/rv64uf/fadd.S @@ -4,7 +4,7 @@ # fadd.S #----------------------------------------------------------------------------- # -# Test f{add|sub|mul}.{s|d} instructions. +# Test f{add|sub|mul}.s instructions. # #include "riscv_test.h" @@ -21,29 +21,16 @@ RVTEST_CODE_BEGIN TEST_FP_OP2_S( 3, fadd.s, 1, -1234, -1235.1, 1.1 ); TEST_FP_OP2_S( 4, fadd.s, 1, 3.14159265, 3.14159265, 0.00000001 ); - TEST_FP_OP2_D( 5, fadd.d, 0, 3.5, 2.5, 1.0 ); - TEST_FP_OP2_D( 6, fadd.d, 1, -1234, -1235.1, 1.1 ); - TEST_FP_OP2_D( 7, fadd.d, 1, 3.14159266, 3.14159265, 0.00000001 ); + TEST_FP_OP2_S( 5, fsub.s, 0, 1.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 6, fsub.s, 1, -1234, -1235.1, -1.1 ); + TEST_FP_OP2_S( 7, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 ); - TEST_FP_OP2_S(12, fsub.s, 0, 1.5, 2.5, 1.0 ); - TEST_FP_OP2_S(13, fsub.s, 1, -1234, -1235.1, -1.1 ); - TEST_FP_OP2_S(14, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 ); - - TEST_FP_OP2_D(15, fsub.d, 0, 1.5, 2.5, 1.0 ); - TEST_FP_OP2_D(16, fsub.d, 1, -1234, -1235.1, -1.1 ); - TEST_FP_OP2_D(17, fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 ); - - TEST_FP_OP2_S(22, fmul.s, 0, 2.5, 2.5, 1.0 ); - TEST_FP_OP2_S(23, fmul.s, 1, 1358.61, -1235.1, -1.1 ); - TEST_FP_OP2_S(24, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); - - TEST_FP_OP2_D(25, fmul.d, 0, 2.5, 2.5, 1.0 ); - TEST_FP_OP2_D(26, fmul.d, 1, 1358.61, -1235.1, -1.1 ); - TEST_FP_OP2_D(27, fmul.d, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); + TEST_FP_OP2_S( 8, fmul.s, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 9, fmul.s, 1, 1358.61, -1235.1, -1.1 ); + TEST_FP_OP2_S(10, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); # Is the canonical NaN generated for Inf - Inf? - TEST_FP_OP2_S(28, fsub.s, 0x10, 0f:7fc00000, Inf, Inf); - TEST_FP_OP2_D(29, fsub.d, 0x10, 0d:7ff8000000000000, Inf, Inf); + TEST_FP_OP2_S(11, fsub.s, 0x10, 0f:7fc00000, Inf, Inf); TEST_PASSFAIL diff --git a/isa/rv64uf/fclass.S b/isa/rv64uf/fclass.S index bcebbf8..5a6361e 100644 --- a/isa/rv64uf/fclass.S +++ b/isa/rv64uf/fclass.S @@ -4,7 +4,7 @@ # fclass.S #----------------------------------------------------------------------------- # -# Test fclass.{s|d} instructions. +# Test fclass.s instructions. # #include "riscv_test.h" @@ -32,21 +32,6 @@ RVTEST_CODE_BEGIN TEST_FCLASS_S(10, 1 << 8, 0x7f800001 ) TEST_FCLASS_S(11, 1 << 9, 0x7fc00000 ) - #define TEST_FCLASS_D(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ - fclass.d a0, fa0) - - TEST_FCLASS_D(12, 1 << 0, 0xfff0000000000000 ) - TEST_FCLASS_D(13, 1 << 1, 0xbff0000000000000 ) - TEST_FCLASS_D(14, 1 << 2, 0x800fffffffffffff ) - TEST_FCLASS_D(15, 1 << 3, 0x8000000000000000 ) - TEST_FCLASS_D(16, 1 << 4, 0x0000000000000000 ) - TEST_FCLASS_D(17, 1 << 5, 0x000fffffffffffff ) - TEST_FCLASS_D(18, 1 << 6, 0x3ff0000000000000 ) - TEST_FCLASS_D(19, 1 << 7, 0x7ff0000000000000 ) - TEST_FCLASS_D(20, 1 << 8, 0x7ff0000000000001 ) - TEST_FCLASS_D(21, 1 << 9, 0x7ff8000000000000 ) - TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64uf/fcmp.S b/isa/rv64uf/fcmp.S index 252ad29..24b08c7 100644 --- a/isa/rv64uf/fcmp.S +++ b/isa/rv64uf/fcmp.S @@ -4,7 +4,7 @@ # fcmp.S #----------------------------------------------------------------------------- # -# Test f{eq|lt|le}.{s|d} instructions. +# Test f{eq|lt|le}.s instructions. # #include "riscv_test.h" diff --git a/isa/rv64uf/fcvt.S b/isa/rv64uf/fcvt.S index cbaf6d3..7bcb49a 100644 --- a/isa/rv64uf/fcvt.S +++ b/isa/rv64uf/fcvt.S @@ -4,7 +4,7 @@ # fcvt.S #----------------------------------------------------------------------------- # -# Test fcvt.{s|d}.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. +# Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. # #include "riscv_test.h" @@ -29,30 +29,6 @@ RVTEST_CODE_BEGIN TEST_INT_FP_OP_S( 8, fcvt.s.lu, 2.0, 2); TEST_INT_FP_OP_S( 9, fcvt.s.lu, 1.8446744e19, -2); - TEST_INT_FP_OP_D(12, fcvt.d.w, 2.0, 2); - TEST_INT_FP_OP_D(13, fcvt.d.w, -2.0, -2); - - TEST_INT_FP_OP_D(14, fcvt.d.wu, 2.0, 2); - TEST_INT_FP_OP_D(15, fcvt.d.wu, 4294967294, -2); - - TEST_INT_FP_OP_D(16, fcvt.d.l, 2.0, 2); - TEST_INT_FP_OP_D(17, fcvt.d.l, -2.0, -2); - - TEST_INT_FP_OP_D(18, fcvt.d.lu, 2.0, 2); - TEST_INT_FP_OP_D(19, fcvt.d.lu, 1.8446744073709552e19, -2); - - TEST_FCVT_S_D(20, -1.5, -1.5) - TEST_FCVT_D_S(21, -1.5, -1.5) - - TEST_CASE(22, a0, 0x7ff8000000000000, - la a1, test_data_22; - ld a2, 0(a1); - fmv.d.x f2, a2; - fcvt.s.d f2, f2; - fcvt.d.s f2, f2; - fmv.x.d a0, f2; - ) - TEST_PASSFAIL RVTEST_CODE_END @@ -62,7 +38,4 @@ RVTEST_DATA_BEGIN TEST_DATA -test_data_22: - .dword 0x7ffcffffffff8004 - RVTEST_DATA_END diff --git a/isa/rv64uf/fcvt_w.S b/isa/rv64uf/fcvt_w.S index 7b78eec..92faffa 100644 --- a/isa/rv64uf/fcvt_w.S +++ b/isa/rv64uf/fcvt_w.S @@ -4,7 +4,7 @@ # fcvt_w.S #----------------------------------------------------------------------------- # -# Test fcvt{wu|w|lu|l}.{s|d} instructions. +# Test fcvt{wu|w|lu|l}.s instructions. # #include "riscv_test.h" @@ -50,85 +50,28 @@ RVTEST_CODE_BEGIN TEST_FP_INT_OP_S(37, fcvt.lu.s, 0x01, 1, 1.1, rtz); TEST_FP_INT_OP_S(38, fcvt.lu.s, 0x10, 0, -3e9, rtz); - TEST_FP_INT_OP_D(42, fcvt.w.d, 0x01, -1, -1.1, rtz); - TEST_FP_INT_OP_D(43, fcvt.w.d, 0x00, -1, -1.0, rtz); - TEST_FP_INT_OP_D(44, fcvt.w.d, 0x01, 0, -0.9, rtz); - TEST_FP_INT_OP_D(45, fcvt.w.d, 0x01, 0, 0.9, rtz); - TEST_FP_INT_OP_D(46, fcvt.w.d, 0x00, 1, 1.0, rtz); - TEST_FP_INT_OP_D(47, fcvt.w.d, 0x01, 1, 1.1, rtz); - TEST_FP_INT_OP_D(48, fcvt.w.d, 0x10, -1<<31, -3e9, rtz); - TEST_FP_INT_OP_D(49, fcvt.w.d, 0x10, (1<<31)-1, 3e9, rtz); - - TEST_FP_INT_OP_D(52, fcvt.wu.d, 0x10, 0, -3.0, rtz); - TEST_FP_INT_OP_D(53, fcvt.wu.d, 0x10, 0, -1.0, rtz); - TEST_FP_INT_OP_D(54, fcvt.wu.d, 0x01, 0, -0.9, rtz); - TEST_FP_INT_OP_D(55, fcvt.wu.d, 0x01, 0, 0.9, rtz); - TEST_FP_INT_OP_D(56, fcvt.wu.d, 0x00, 1, 1.0, rtz); - TEST_FP_INT_OP_D(57, fcvt.wu.d, 0x01, 1, 1.1, rtz); - TEST_FP_INT_OP_D(58, fcvt.wu.d, 0x10, 0, -3e9, rtz); - TEST_FP_INT_OP_D(59, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz); - - TEST_FP_INT_OP_D(62, fcvt.l.d, 0x01, -1, -1.1, rtz); - TEST_FP_INT_OP_D(63, fcvt.l.d, 0x00, -1, -1.0, rtz); - TEST_FP_INT_OP_D(64, fcvt.l.d, 0x01, 0, -0.9, rtz); - TEST_FP_INT_OP_D(65, fcvt.l.d, 0x01, 0, 0.9, rtz); - TEST_FP_INT_OP_D(66, fcvt.l.d, 0x00, 1, 1.0, rtz); - TEST_FP_INT_OP_D(67, fcvt.l.d, 0x01, 1, 1.1, rtz); - TEST_FP_INT_OP_D(68, fcvt.l.d, 0x00,-3000000000, -3e9, rtz); - TEST_FP_INT_OP_D(69, fcvt.l.d, 0x00, 3000000000, 3e9, rtz); - TEST_FP_INT_OP_D(60, fcvt.l.d, 0x10, -1<<63,-3e19, rtz); - TEST_FP_INT_OP_D(61, fcvt.l.d, 0x10, (1<<63)-1, 3e19, rtz); - - TEST_FP_INT_OP_D(72, fcvt.lu.d, 0x10, 0, -3.0, rtz); - TEST_FP_INT_OP_D(73, fcvt.lu.d, 0x10, 0, -1.0, rtz); - TEST_FP_INT_OP_D(74, fcvt.lu.d, 0x01, 0, -0.9, rtz); - TEST_FP_INT_OP_D(75, fcvt.lu.d, 0x01, 0, 0.9, rtz); - TEST_FP_INT_OP_D(76, fcvt.lu.d, 0x00, 1, 1.0, rtz); - TEST_FP_INT_OP_D(77, fcvt.lu.d, 0x01, 1, 1.1, rtz); - TEST_FP_INT_OP_D(78, fcvt.lu.d, 0x10, 0, -3e9, rtz); - TEST_FP_INT_OP_D(79, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz); - # test negative NaN, negative infinity conversion - TEST_CASE( 80, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.s x1, f1) - TEST_CASE( 81, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.s x1, f1) - TEST_CASE( 82, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.s x1, f1) - TEST_CASE( 83, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.s x1, f1) - - TEST_CASE( 84, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1) - TEST_CASE( 85, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1) - TEST_CASE( 86, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1) - TEST_CASE( 87, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1) + TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.s x1, f1) + TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.s x1, f1) + TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.s x1, f1) + TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.s x1, f1) # test positive NaN, positive infinity conversion - TEST_CASE( 88, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.s x1, f1) - TEST_CASE( 89, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.s x1, f1) - TEST_CASE( 90, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.s x1, f1) - TEST_CASE( 91, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.s x1, f1) - - TEST_CASE( 92, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1) - TEST_CASE( 93, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1) - TEST_CASE( 94, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1) - TEST_CASE( 95, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1) + TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.s x1, f1) + TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.s x1, f1) + TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.s x1, f1) + TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.s x1, f1) # test NaN, infinity conversions to unsigned integer - TEST_CASE( 96, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.s x1, f1) - TEST_CASE( 97, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.s x1, f1) - TEST_CASE( 98, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.s x1, f1) - TEST_CASE( 99, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.s x1, f1) - TEST_CASE(100, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.s x1, f1) - TEST_CASE(101, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.s x1, f1) - TEST_CASE(102, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.s x1, f1) - TEST_CASE(103, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.s x1, f1) + TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.s x1, f1) + TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.s x1, f1) + TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.s x1, f1) + TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.s x1, f1) + TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.s x1, f1) + TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.s x1, f1) + TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.s x1, f1) + TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.s x1, f1) - TEST_CASE(104, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1) - TEST_CASE(105, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1) - TEST_CASE(106, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1) - TEST_CASE(107, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1) - TEST_CASE(108, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1) - TEST_CASE(109, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1) - TEST_CASE(110, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1) - TEST_CASE(111, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1) - TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64uf/fdiv.S b/isa/rv64uf/fdiv.S index 688f635..a75a23d 100644 --- a/isa/rv64uf/fdiv.S +++ b/isa/rv64uf/fdiv.S @@ -4,7 +4,7 @@ # fdiv.S #----------------------------------------------------------------------------- # -# Test f{div|sqrt}.{s|d} instructions. +# Test f{div|sqrt}.s instructions. # #include "riscv_test.h" @@ -17,27 +17,16 @@ RVTEST_CODE_BEGIN # Arithmetic tests #------------------------------------------------------------- - TEST_FP_OP2_S( 2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); - TEST_FP_OP2_S( 3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 ); - TEST_FP_OP2_S( 4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 ); + TEST_FP_OP2_S(2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_S(3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_S(4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 ); - TEST_FP_OP2_D( 5, fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); - TEST_FP_OP2_D( 6, fdiv.d, 1,-0.9991093838555584, -1234, 1235.1 ); - TEST_FP_OP2_D( 7, fdiv.d, 0, 3.14159265, 3.14159265, 1.0 ); + TEST_FP_OP1_S(5, fsqrt.s, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_S(6, fsqrt.s, 0, 100, 10000 ); - TEST_FP_OP1_S(11, fsqrt.s, 1, 1.7724538498928541, 3.14159265 ); - TEST_FP_OP1_S(12, fsqrt.s, 0, 100, 10000 ); + TEST_FP_OP1_S_DWORD_RESULT(7, fsqrt.s, 0x10, 0x7FC00000, -1.0 ); - TEST_FP_OP1_D(13, fsqrt.d, 1, 1.7724538498928541, 3.14159265 ); - TEST_FP_OP1_D(14, fsqrt.d, 0, 100, 10000 ); - - TEST_FP_OP1_S_DWORD_RESULT(15, fsqrt.s, 0x10, 0x7FC00000, -1.0 ); - TEST_FP_OP1_D_DWORD_RESULT(16, fsqrt.d, 0x10, 0x7FF8000000000000, -1.0 ); - - TEST_FP_OP1_S(17, fsqrt.s, 1, 13.076696, 171.0); - TEST_FP_OP1_D(18, fsqrt.d, 1, 13.076696830622021, 171.0); - - TEST_FP_OP1_D(19, fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7); + TEST_FP_OP1_S(8, fsqrt.s, 1, 13.076696, 171.0); TEST_PASSFAIL diff --git a/isa/rv64uf/fmadd.S b/isa/rv64uf/fmadd.S index 62ea102..241bead 100644 --- a/isa/rv64uf/fmadd.S +++ b/isa/rv64uf/fmadd.S @@ -21,33 +21,17 @@ RVTEST_CODE_BEGIN TEST_FP_OP3_S( 3, fmadd.s, 1, 1236.2, -1.0, -1235.1, 1.1 ); TEST_FP_OP3_S( 4, fmadd.s, 0, -12.0, 2.0, -5.0, -2.0 ); - TEST_FP_OP3_D( 5, fmadd.d, 0, 3.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_D( 6, fmadd.d, 1, 1236.1999999999999, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_D( 7, fmadd.d, 0, -12.0, 2.0, -5.0, -2.0 ); + TEST_FP_OP3_S( 5, fnmadd.s, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 6, fnmadd.s, 1, -1236.2, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S( 7, fnmadd.s, 0, 12.0, 2.0, -5.0, -2.0 ); - TEST_FP_OP3_S( 8, fnmadd.s, 0, -3.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_S( 9, fnmadd.s, 1, -1236.2, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_S(10, fnmadd.s, 0, 12.0, 2.0, -5.0, -2.0 ); + TEST_FP_OP3_S( 8, fmsub.s, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 9, fmsub.s, 1, 1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S(10, fmsub.s, 0, -8.0, 2.0, -5.0, -2.0 ); - TEST_FP_OP3_D(11, fnmadd.d, 0, -3.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_D(12, fnmadd.d, 1, -1236.1999999999999, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_D(13, fnmadd.d, 0, 12.0, 2.0, -5.0, -2.0 ); - - TEST_FP_OP3_S(14, fmsub.s, 0, 1.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_S(15, fmsub.s, 1, 1234, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_S(16, fmsub.s, 0, -8.0, 2.0, -5.0, -2.0 ); - - TEST_FP_OP3_D(17, fmsub.d, 0, 1.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_D(18, fmsub.d, 1, 1234, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_D(19, fmsub.d, 0, -8.0, 2.0, -5.0, -2.0 ); - - TEST_FP_OP3_S(20, fnmsub.s, 0, -1.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_S(21, fnmsub.s, 1, -1234, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_S(22, fnmsub.s, 0, 8.0, 2.0, -5.0, -2.0 ); - - TEST_FP_OP3_D(23, fnmsub.d, 0, -1.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_D(24, fnmsub.d, 1, -1234, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_D(25, fnmsub.d, 0, 8.0, 2.0, -5.0, -2.0 ); + TEST_FP_OP3_S(11, fnmsub.s, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S(12, fnmsub.s, 1, -1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S(13, fnmsub.s, 0, 8.0, 2.0, -5.0, -2.0 ); TEST_PASSFAIL diff --git a/isa/rv64uf/fmin.S b/isa/rv64uf/fmin.S index 56a6e7b..a2650e5 100644 --- a/isa/rv64uf/fmin.S +++ b/isa/rv64uf/fmin.S @@ -4,7 +4,7 @@ # fmin.S #----------------------------------------------------------------------------- # -# Test f{min|max}.{s|d} instructinos. +# Test f{min|max}.s instructinos. # #include "riscv_test.h" @@ -31,20 +31,6 @@ RVTEST_CODE_BEGIN TEST_FP_OP2_S(16, fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 ); TEST_FP_OP2_S(17, fmax.s, 0, -1.0, -1.0, -2.0 ); - TEST_FP_OP2_D(22, fmin.d, 0, 1.0, 2.5, 1.0 ); - TEST_FP_OP2_D(23, fmin.d, 0, -1235.1, -1235.1, 1.1 ); - TEST_FP_OP2_D(24, fmin.d, 0, -1235.1, 1.1, -1235.1 ); - TEST_FP_OP2_D(25, fmin.d, 0, -1235.1, NaN, -1235.1 ); - TEST_FP_OP2_D(26, fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 ); - TEST_FP_OP2_D(27, fmin.d, 0, -2.0, -1.0, -2.0 ); - - TEST_FP_OP2_D(32, fmax.d, 0, 2.5, 2.5, 1.0 ); - TEST_FP_OP2_D(33, fmax.d, 0, 1.1, -1235.1, 1.1 ); - TEST_FP_OP2_D(34, fmax.d, 0, 1.1, 1.1, -1235.1 ); - TEST_FP_OP2_D(35, fmax.d, 0, -1235.1, NaN, -1235.1 ); - TEST_FP_OP2_D(36, fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 ); - TEST_FP_OP2_D(37, fmax.d, 0, -1.0, -1.0, -2.0 ); - TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64uf/fsgnj.S b/isa/rv64uf/fsgnj.S index 68d5ee6..6d4bdb4 100644 --- a/isa/rv64uf/fsgnj.S +++ b/isa/rv64uf/fsgnj.S @@ -4,7 +4,7 @@ # fsgnj.S #----------------------------------------------------------------------------- # -# Test fsgn{j|jn|x}.{s|d} instructions. +# Test fsgn{j|jn|x}.s instructions. # #include "riscv_test.h" @@ -32,21 +32,6 @@ RVTEST_CODE_BEGIN TEST_FP_OP2_S(24, fsgnjx.s, 0, 8.3, -8.3, -3.0 ); TEST_FP_OP2_S(25, fsgnjx.s, 0, -9.3, -9.3, 4.0 ); - TEST_FP_OP2_D(32, fsgnj.d, 0, -6.3, 6.3, -1.0 ); - TEST_FP_OP2_D(33, fsgnj.d, 0, 7.3, 7.3, 2.0 ); - TEST_FP_OP2_D(34, fsgnj.d, 0, -8.3, -8.3, -3.0 ); - TEST_FP_OP2_D(35, fsgnj.d, 0, 9.3, -9.3, 4.0 ); - - TEST_FP_OP2_D(42, fsgnjn.d, 0, 6.3, 6.3, -1.0 ); - TEST_FP_OP2_D(43, fsgnjn.d, 0, -7.3, 7.3, 2.0 ); - TEST_FP_OP2_D(44, fsgnjn.d, 0, 8.3, -8.3, -3.0 ); - TEST_FP_OP2_D(45, fsgnjn.d, 0, -9.3, -9.3, 4.0 ); - - TEST_FP_OP2_D(52, fsgnjx.d, 0, -6.3, 6.3, -1.0 ); - TEST_FP_OP2_D(53, fsgnjx.d, 0, 7.3, 7.3, 2.0 ); - TEST_FP_OP2_D(54, fsgnjx.d, 0, 8.3, -8.3, -3.0 ); - TEST_FP_OP2_D(55, fsgnjx.d, 0, -9.3, -9.3, 4.0 ); - TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64uf/ldst.S b/isa/rv64uf/ldst.S index 63123f2..c35dd8d 100644 --- a/isa/rv64uf/ldst.S +++ b/isa/rv64uf/ldst.S @@ -15,8 +15,6 @@ RVTEST_CODE_BEGIN TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1)) TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1)) - TEST_CASE(4, a0, 0x40000000bf800000, la a1, tdat; fld f2, 0(a1); fsd f2, 16(a1); ld a0, 16(a1)) - TEST_CASE(5, a0, 0xc080000040400000, la a1, tdat; fld f2, 8(a1); fsd f2, 16(a1); ld a0, 16(a1)) TEST_PASSFAIL diff --git a/isa/rv64uf/move.S b/isa/rv64uf/move.S index 53b8cf3..a94af55 100644 --- a/isa/rv64uf/move.S +++ b/isa/rv64uf/move.S @@ -5,7 +5,7 @@ #----------------------------------------------------------------------------- # # This test verifies that mxtf.[s,d], mftx.[s,d], fssr, frsr, -# and fsgnj[x|n].[s|d] work properly. +# and fsgnj[x|n].s work properly. # #include "riscv_test.h" @@ -22,12 +22,10 @@ fssr a0 TEST_CASE(4, a0, 0x34, frsr a0) TEST_CASE(5, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fmv.x.s a0, f0) - TEST_CASE(6, a0, 0x3FF02468A0000000, li a1, 0x3FF02468A0000000; fmv.d.x f1, a1; fmv.x.d a0, f1) - TEST_CASE(7, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fsgnj.s f1, f0, f0; fmv.x.s a0, f1) - TEST_CASE(8, a0, 0x000000004BA98765, li a1, 0xFFFFFFFFCBA98765; fmv.s.x f0, a1; fsgnjx.s f1, f0, f0; fmv.x.s a0, f1) - TEST_CASE(9, a0, 0x000000005EADBEEF, li a1, 0xFFFFFFFFDEADBEEF; fmv.s.x f0, a1; fsgnjn.s f1, f0, f0; fmv.x.s a0, f1) - TEST_CASE(10, a0, 0xBFF02468A0001000, li a1, 0x3FF02468A0001000; li a2, -1; fmv.d.x f1, a1; fmv.d.x f2, a2; fsgnj.d f0, f1, f2; fmv.x.d a0, f0) + TEST_CASE(6, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fsgnj.s f1, f0, f0; fmv.x.s a0, f1) + TEST_CASE(7, a0, 0x000000004BA98765, li a1, 0xFFFFFFFFCBA98765; fmv.s.x f0, a1; fsgnjx.s f1, f0, f0; fmv.x.s a0, f1) + TEST_CASE(8, a0, 0x000000005EADBEEF, li a1, 0xFFFFFFFFDEADBEEF; fmv.s.x f0, a1; fsgnjn.s f1, f0, f0; fmv.x.s a0, f1) TEST_PASSFAIL diff --git a/isa/rv64uf/recoding.S b/isa/rv64uf/recoding.S index 2ab17e2..802be66 100644 --- a/isa/rv64uf/recoding.S +++ b/isa/rv64uf/recoding.S @@ -25,31 +25,13 @@ RVTEST_CODE_BEGIN TEST_CASE( 4, a0, 0, flt.s a0, f0, f1) # Likewise, but for zeroes. - fcvt.d.w f0, x0 + fcvt.s.w f0, x0 li a0, 1 - fcvt.d.w f1, a0 - fmul.d f1, f1, f0 - TEST_CASE(5, a0, 1, feq.d a0, f0, f1) - TEST_CASE(6, a0, 1, fle.d a0, f0, f1) - TEST_CASE(7, a0, 0, flt.d a0, f0, f1) - - # When converting small doubles to single-precision subnormals, - # ensure that the extra precision is discarded. - flw f0, big, a0 - fld f1, tiny, a0 - fcvt.s.d f1, f1 - fmul.s f0, f0, f1 - fmv.x.s a0, f0 - lw a1, small - TEST_CASE(10, a0, 0, sub a0, a0, a1) - - # Make sure FSD+FLD correctly saves and restores a single-precision value. - flw f0, three, a0 - fadd.s f1, f0, f0 - fadd.s f0, f0, f0 - fsd f0, tiny, a0 - fld f0, tiny, a0 - TEST_CASE(20, a0, 1, feq.s a0, f0, f1) + fcvt.s.w f1, a0 + fmul.s f1, f1, f0 + TEST_CASE(5, a0, 1, feq.s a0, f0, f1) + TEST_CASE(6, a0, 1, fle.s a0, f0, f1) + TEST_CASE(7, a0, 0, flt.s a0, f0, f1) TEST_PASSFAIL @@ -60,8 +42,5 @@ RVTEST_DATA_BEGIN minf: .float -Inf three: .float 3.0 -big: .float 1221 -small: .float 2.9133121e-37 -tiny: .double 2.3860049081905093e-40 RVTEST_DATA_END diff --git a/isa/rv64uf/structural.S b/isa/rv64uf/structural.S deleted file mode 100644 index 76c6691..0000000 --- a/isa/rv64uf/structural.S +++ /dev/null @@ -1,58 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# structural.S -#----------------------------------------------------------------------------- -# -# This test verifies that the FPU correctly obviates structural hazards on its -# writeback port (e.g. fadd followed by fsgnj) -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UF -RVTEST_CODE_BEGIN - -li x25, 1 - -li x2, 0x3FF0000000000000 -li x1, 0x3F800000 - -#define TEST(nops, errcode) \ - fmv.d.x f4, x0 ;\ - fmv.s.x f3, x0 ;\ - fmv.d.x f2, x2 ;\ - fmv.s.x f1, x1 ;\ - j 1f ;\ - .align 5 ;\ -1:fmul.d f4, f2, f2 ;\ - nops ;\ - fsgnj.s f3, f1, f1 ;\ - fmv.x.d x4, f4 ;\ - fmv.x.s x3, f3 ;\ - beq x1, x3, 2f ;\ - RVTEST_FAIL ;\ -2:beq x2, x4, 2f ;\ - RVTEST_FAIL; \ -2:fmv.d.x f2, zero ;\ - fmv.s.x f1, zero ;\ - -TEST(;,2) -TEST(nop,4) -TEST(nop;nop,6) -TEST(nop;nop;nop,8) -TEST(nop;nop;nop;nop,10) -TEST(nop;nop;nop;nop;nop,12) -TEST(nop;nop;nop;nop;nop;nop,14) - -RVTEST_PASS - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END