From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 17:38:07 +0000 (-0700)
Subject: Fix typo and comments
X-Git-Tag: working-ls180~1208^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;ds=sidebyside;h=c8649953431d3789296c4a7c1bd559ec136af6e3;p=yosys.git

Fix typo and comments
---

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index d3f6a60cc..233a56003 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -204,7 +204,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
     end
     else if (A_WIDTH <= 4) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" status to get lost, extend with MSB
+      // causing the "don't care" status to get lost, extend with MSBs
       // so that we can recognise again later when mapping MUXF78
       wire [4-1:0] Ax;
       if (A_WIDTH == 4)
@@ -215,7 +215,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
     end
     else if (A_WIDTH <= 8) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" status to get lost, extend with MSB
+      // causing the "don't care" status to get lost, extend with MSBs
       // so that we can recognise again later when mapping MUXF78
       wire [8-1:0] Ax;
       if (A_WIDTH == 8)
@@ -230,13 +230,13 @@ module \$__XILINX_SHIFTX (A, B, Y);
     end
     else if (A_WIDTH <= 16) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" status to get lost, extend with MSB
+      // causing the "don't care" status to get lost, extend with MSBs
       // so that we can recognise again later when mapping MUXF78
       wire [16-1:0] Ax;
       if (A_WIDTH == 16)
         assign Ax = A;
       else
-        assign Ax = {A[7-:8-A_WIDTH], A};
+        assign Ax = {A[7-:16-A_WIDTH], A};
       wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
                      : B[3] ? Ax[ 8] : Ax[0];
       wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]