From: Michael Nolan <mtnolan2640@gmail.com>
Date: Tue, 19 May 2020 19:26:48 +0000 (-0400)
Subject: Begin adding trap FU
X-Git-Tag: div_pipeline~1072
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=000ac6e00d86b426a466dba9e7d322e70c5b5246;p=soc.git

Begin adding trap FU
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
new file mode 100644
index 00000000..86fa8c84
--- /dev/null
+++ b/src/soc/fu/trap/main_stage.py
@@ -0,0 +1,39 @@
+
+from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
+from nmutil.pipemodbase import PipeModBase
+from nmutil.clz import CLZ
+from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
+from soc.decoder.power_enums import InternalOp
+
+from soc.decoder.power_fields import DecodeFields
+from soc.decoder.power_fieldsn import SignalBitRange
+
+
+def array_of(count, bitwidth):
+    res = []
+    for i in range(count):
+        res.append(Signal(bitwidth, reset_less=True))
+    return res
+
+
+class LogicalMainStage(PipeModBase):
+    def __init__(self, pspec):
+        super().__init__(pspec, "main")
+        self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
+        self.fields.create_specs()
+
+    def ispec(self):
+        return TrapInputData(self.pspec)
+
+    def ospec(self):
+        return TrapOutputData(self.pspec)
+
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+        op, a, b = self.i.ctx.op, self.i.a, self.i.b
+
+
+        comb += self.o.ctx.eq(self.i.ctx)
+
+        return m
diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
new file mode 100644
index 00000000..42548952
--- /dev/null
+++ b/src/soc/fu/trap/pipe_data.py
@@ -0,0 +1,45 @@
+from nmigen import Signal, Const
+from ieee754.fpcommon.getop import FPPipeContext
+from soc.fu.alu.pipe_data import IntegerData
+
+
+class TrapInputData(IntegerData):
+    def __init__(self, pspec):
+        super().__init__(pspec)
+        self.a = Signal(64, reset_less=True)  # RA
+        self.b = Signal(64, reset_less=True)  # RB/immediate
+        self.cia = Signal(64, reset_less=True)  # Program counter
+        self.msr = Signal(64, reset_less=True)  # MSR
+
+    def __iter__(self):
+        yield from super().__iter__()
+        yield self.a
+        yield self.b
+        yield self.cia
+        yield self.msr
+
+    def eq(self, i):
+        lst = super().eq(i)
+        return lst + [self.a.eq(i.a), self.b.eq(i.b),
+                      self.cia.eq(i.nia), self.msr.eq(i.msr)]
+
+class TrapOutputData(IntegerData):
+    def __init__(self, pspec):
+        super().__init__(pspec)
+        self.nia = Signal(64, reset_less=True) # RA
+        self.msr = Signal(64, reset_less=True) # RB/immediate
+        self.srr0 = Signal(64, reset_less=True) # RB/immediate
+        self.srr1 = Signal(64, reset_less=True) # RB/immediate
+
+    def __iter__(self):
+        yield from super().__iter__()
+        yield self.nia
+        yield self.msr
+        yield self.srr0
+        yield self.srr1
+
+    def eq(self, i):
+        lst = super().eq(i)
+        return lst + [
+            self.nia.eq(i.nia), self.msr.eq(i.msr),
+            self.srr0.eq(i.srr0), self.srr1.eq(i.srr1)]