From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 19:00:39 +0000 (-0700)
Subject: Add more entries
X-Git-Tag: working-ls180~1039^2~95
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0020a18929c30744eae4960ab97f6ebefc32a154;p=yosys.git

Add more entries
---

diff --git a/CHANGELOG b/CHANGELOG
index 8d7dd3e19..8ee73771f 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -41,6 +41,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
     - Added "-match-init" option to "dff2dffs" pass
     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
+    - Added "ice40_dsp" for Lattice iCE40 DSP packing
     - Added "xilinx_dsp" for Xilinx DSP packing
     - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
     - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)