From: Luke Kenneth Casson Leighton Date: Tue, 23 Jul 2019 21:44:25 +0000 (+0100) Subject: reduce am0/bm0 by 2 bits in DIV X-Git-Tag: ls180-24jan2020~738 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0029776bf60017b5e9cba28684e3d69474ff2e7a;p=ieee754fpu.git reduce am0/bm0 by 2 bits in DIV --- diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py index 3c6c0b1f..91baea6b 100644 --- a/src/ieee754/fpdiv/div0.py +++ b/src/ieee754/fpdiv/div0.py @@ -83,8 +83,8 @@ class FPDivStage0Mod(Elaboratable): # DIV with m.If(self.i.ctx.op == 0): - am0 = Signal(len(self.i.a.m)+3, reset_less=True) - bm0 = Signal(len(self.i.b.m)+3, reset_less=True) + am0 = Signal(len(self.i.a.m)+1, reset_less=True) + bm0 = Signal(len(self.i.b.m)+1, reset_less=True) m.d.comb += [ am0.eq(Cat(self.i.a.m, 0)), bm0.eq(Cat(self.i.b.m, 0)),