From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 8 Jan 2024 22:37:02 +0000 (+0000)
Subject: bug 676: sorting out maxloc assembler, found bug in sv.creqv vector
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=003115d89d976218dd9e79bc986a44c5340fffae;p=openpower-isa.git

bug 676: sorting out maxloc assembler, found bug in sv.creqv vector
raised https://bugs.libre-soc.org/show_bug.cgi?id=1248
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index c6f255ba..3e799eb6 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -2679,10 +2679,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             # if there was not an explicit CR0 in the pseudocode,
             # do implicit Rc=1
             c = self.handle_comparison(result, regnum, overflow, no_so=is_setvl)
-            log("implicit cr0", c)
+            log("implicit cr0 %d" % regnum, c)
         else:
             # otherwise we just blat CR0 into the required regnum
-            log("explicit cr0", cr0)
+            log("explicit cr0 %d" % regnum, cr0)
             self.crl[regnum].eq(cr0)
 
     def do_outregs(self, info, outs, ca_en, ffirst_hit, ew_dst, outs_ok):
diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
index 25ce646f..3a384499 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
@@ -17,6 +17,7 @@ from openpower.decoder.selectable_int import SelectableInt
 from openpower.simulator.program import Program
 from openpower.insndb.asm import SVP64Asm
 from openpower.util import log
+from openpower.decoder.isa.maxloc import m2
 
 
 
@@ -54,7 +55,7 @@ class DDFFirstTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_maxloc_1(self):
-        self.sv_maxloc([1,2,3,0])
+        self.sv_maxloc([0,6,1,7])
 
     def tst_sv_maxloc_2(self):
         self.sv_maxloc([3,4,1,5])
@@ -85,14 +86,17 @@ class DDFFirstTestCase(FHDLTestCase):
                 #"addi 6, 0, 0",             # initialise r6 to zero
                 #"sv.lbzu/pi/dw=8 *6, 1(4)", # should be /lf here as well
                 # while (i<n and a[i]<=m) : i += 1
-                "sv.minmax./ff=ge *5, *10, *4, 1", # scalar RB=RT
+                "sv.minmax./ff=ge/m=ge *5, *10, *4, 1", # scalar RB=RT
                 "sv.mcrf/m=ge *4,*0", # masked-copy CR0-CR3 to CR4-CR7
                 "setvl 3,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
                 "sv.addi/mr/m=lt 4, *5, 0", # r4 = last non-masked value
-                "sv.minmax./ff=lt/m=ge 4, *10, 4, 1", # scalar RB=RT
+                "mtcrf 128, 0",       # clear CR0
+                "sv.minmax./ff=lt/m=ge/vli 4, *10, 4, 1", # scalar RB=RT
                 "sv.svstep/mr 2, 0, 6, 1",  # svstep: get vector dststep
-                "setvl 3,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
-                "sv.bc/all/m=ge 16, 19, -0x38", # until r10[i]>r4 (and dec CTR)
+                "sv.creqv *16,*16,*16", # masked-copy CR0-CR3 to CR4-CR7
+                "bc 12,0, -0x3c"            # CR0 lt bit clear, branch back
+                #"setvl 3,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
+                #"sv.bc/all/m=ge 16, 19, -0x3c", # until r10[i]>r4 (and dec CTR)
                         ])
         lst = list(lst)