From: Tushar Krishna Date: Thu, 6 Oct 2016 18:35:18 +0000 (-0400) Subject: config: make internal links in network topology unidirectional. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=003c08fa90f8b3eb7fbbbc96e0caa5f46bf58196;p=gem5.git config: make internal links in network topology unidirectional. This patch makes the internal links within the network topology unidirectional, thus allowing any deadlock-free routing algorithms to be specified from the topology itself using weights. This patch also renames Mesh.py and MeshDirCorners.py to Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing). It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies. --- diff --git a/configs/topologies/Cluster.py b/configs/topologies/Cluster.py index b146d8675..fad90856d 100644 --- a/configs/topologies/Cluster.py +++ b/configs/topologies/Cluster.py @@ -86,23 +86,30 @@ class Cluster(BaseTopology): node.makeTopology(options, network, IntLink, ExtLink, Router) # connect this cluster to the router - link = IntLink(link_id=self.num_int_links(), node_a=self.router, - node_b=node.router) + link_out = IntLink(link_id=self.num_int_links(), src_node=self.router, + dst_node_=node.router) + link_in = IntLink(link_id=self.num_int_links(), src_node=node.router, + dst_node_=self.router) if node.extBW: - link.bandwidth_factor = node.extBW + link_out.bandwidth_factor = node.extBW + link_in.bandwidth_factor = node.extBW - # if there is an interanl b/w for this node + # if there is an internal b/w for this node # and no ext b/w to override elif self.intBW: - link.bandwidth_factor = self.intBW + link_out.bandwidth_factor = self.intBW + link_in.bandwidth_factor = self.intBW if node.extLatency: - link.latency = node.extLatency + link_out.latency = node.extLatency + link_in.latency = node.extLatency elif self.intLatency: - link.latency = self.intLatency + link_out.latency = self.intLatency + link_in.latency = self.intLatency - network.int_links.append(link) + network.int_links.append(link_out) + network.int_links.append(link_in) else: # node is just a controller, # connect it to the router via a ext_link diff --git a/configs/topologies/Crossbar.py b/configs/topologies/Crossbar.py index e3dd431e7..35d20de34 100644 --- a/configs/topologies/Crossbar.py +++ b/configs/topologies/Crossbar.py @@ -39,6 +39,7 @@ class Crossbar(SimpleTopology): # the centralized crossbar. The large numbers of routers are needed # because external links do not model outgoing bandwidth in the # simple network, but internal links do. + # For garnet, one router suffices, use CrossbarGarnet.py routers = [Router(router_id=i) for i in range(len(self.nodes)+1)] xbar = routers[len(self.nodes)] # the crossbar router is the last router created @@ -49,7 +50,18 @@ class Crossbar(SimpleTopology): network.ext_links = ext_links link_count = len(self.nodes) - int_links = [IntLink(link_id=(link_count+i), - node_a=routers[i], node_b=xbar) - for i in range(len(self.nodes))] + + int_links = [] + for i in range(len(self.nodes)): + int_links.append(IntLink(link_id=(link_count+i), + src_node=routers[i], + dst_node=xbar)) + + link_count += len(self.nodes) + + for i in range(len(self.nodes)): + int_links.append(IntLink(link_id=(link_count+i), + src_node=xbar, + dst_node=routers[i])) + network.int_links = int_links diff --git a/configs/topologies/CrossbarGarnet.py b/configs/topologies/CrossbarGarnet.py new file mode 100644 index 000000000..64f8001e2 --- /dev/null +++ b/configs/topologies/CrossbarGarnet.py @@ -0,0 +1,50 @@ +# Copyright (c) 2016 Georgia Institute of Technology +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Tushar Krishna + +from m5.params import * +from m5.objects import * + +from BaseTopology import SimpleTopology + +class CrossbarGarnet(SimpleTopology): + description='CrossbarGarnet' + + def makeTopology(self, options, network, IntLink, ExtLink, Router): + # Create one router in Garnet. Internally models a crossbar and + # the associated allocator. + # For simple network, use Crossbar.py + + xbar = Router(router_id=0) + network.routers = xbar + + ext_links = [ExtLink(link_id=i, ext_node=n, int_node=xbar) + for (i, n) in enumerate(self.nodes)] + network.ext_links = ext_links + + int_links = [] + network.int_links = int_links diff --git a/configs/topologies/Mesh.py b/configs/topologies/Mesh.py deleted file mode 100644 index 446fc4a18..000000000 --- a/configs/topologies/Mesh.py +++ /dev/null @@ -1,117 +0,0 @@ -# Copyright (c) 2010 Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Brad Beckmann - -from m5.params import * -from m5.objects import * - -from BaseTopology import SimpleTopology - -class Mesh(SimpleTopology): - description='Mesh' - - def __init__(self, controllers): - self.nodes = controllers - - # Makes a generic mesh assuming an equal number of cache and directory cntrls - - def makeTopology(self, options, network, IntLink, ExtLink, Router): - nodes = self.nodes - - num_routers = options.num_cpus - num_rows = options.mesh_rows - - # There must be an evenly divisible number of cntrls to routers - # Also, obviously the number or rows must be <= the number of routers - cntrls_per_router, remainder = divmod(len(nodes), num_routers) - assert(num_rows <= num_routers) - num_columns = int(num_routers / num_rows) - assert(num_columns * num_rows == num_routers) - - # Create the routers in the mesh - routers = [Router(router_id=i) for i in range(num_routers)] - network.routers = routers - - # link counter to set unique link ids - link_count = 0 - - # Add all but the remainder nodes to the list of nodes to be uniformly - # distributed across the network. - network_nodes = [] - remainder_nodes = [] - for node_index in xrange(len(nodes)): - if node_index < (len(nodes) - remainder): - network_nodes.append(nodes[node_index]) - else: - remainder_nodes.append(nodes[node_index]) - - # Connect each node to the appropriate router - ext_links = [] - for (i, n) in enumerate(network_nodes): - cntrl_level, router_id = divmod(i, num_routers) - assert(cntrl_level < cntrls_per_router) - ext_links.append(ExtLink(link_id=link_count, ext_node=n, - int_node=routers[router_id])) - link_count += 1 - - # Connect the remainding nodes to router 0. These should only be - # DMA nodes. - for (i, node) in enumerate(remainder_nodes): - assert(node.type == 'DMA_Controller') - assert(i < remainder) - ext_links.append(ExtLink(link_id=link_count, ext_node=node, - int_node=routers[0])) - link_count += 1 - - network.ext_links = ext_links - - # Create the mesh links. First row (east-west) links then column - # (north-south) links - int_links = [] - for row in xrange(num_rows): - for col in xrange(num_columns): - if (col + 1 < num_columns): - east_id = col + (row * num_columns) - west_id = (col + 1) + (row * num_columns) - int_links.append(IntLink(link_id=link_count, - node_a=routers[east_id], - node_b=routers[west_id], - weight=1)) - link_count += 1 - - for col in xrange(num_columns): - for row in xrange(num_rows): - if (row + 1 < num_rows): - north_id = col + (row * num_columns) - south_id = col + ((row + 1) * num_columns) - int_links.append(IntLink(link_id=link_count, - node_a=routers[north_id], - node_b=routers[south_id], - weight=2)) - link_count += 1 - - network.int_links = int_links diff --git a/configs/topologies/MeshDirCorners.py b/configs/topologies/MeshDirCorners.py deleted file mode 100644 index 40720004e..000000000 --- a/configs/topologies/MeshDirCorners.py +++ /dev/null @@ -1,138 +0,0 @@ -# Copyright (c) 2010 Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Brad Beckmann - -from m5.params import * -from m5.objects import * - -from BaseTopology import SimpleTopology - -class MeshDirCorners(SimpleTopology): - description='MeshDirCorners' - - def __init__(self, controllers): - self.nodes = controllers - - # This file contains a special network creation function. This - # networks is not general and will only work with specific system - # configurations. The network specified is similar to GEMS old file - # specified network. - - def makeTopology(self, options, network, IntLink, ExtLink, Router): - nodes = self.nodes - - num_routers = options.num_cpus - num_rows = options.mesh_rows - - # First determine which nodes are cache cntrls vs. dirs vs. dma - cache_nodes = [] - dir_nodes = [] - dma_nodes = [] - for node in nodes: - if node.type == 'L1Cache_Controller' or \ - node.type == 'L2Cache_Controller': - cache_nodes.append(node) - elif node.type == 'Directory_Controller': - dir_nodes.append(node) - elif node.type == 'DMA_Controller': - dma_nodes.append(node) - - # Obviously the number or rows must be <= the number of routers - # and evenly divisible. Also the number of caches must be a - # multiple of the number of routers and the number of directories - # must be four. - assert(num_rows <= num_routers) - num_columns = int(num_routers / num_rows) - assert(num_columns * num_rows == num_routers) - caches_per_router, remainder = divmod(len(cache_nodes), num_routers) - assert(remainder == 0) - assert(len(dir_nodes) == 4) - - # Create the routers in the mesh - routers = [Router(router_id=i) for i in range(num_routers)] - network.routers = routers - - # link counter to set unique link ids - link_count = 0 - - # Connect each cache controller to the appropriate router - ext_links = [] - for (i, n) in enumerate(cache_nodes): - cntrl_level, router_id = divmod(i, num_routers) - assert(cntrl_level < caches_per_router) - ext_links.append(ExtLink(link_id=link_count, ext_node=n, - int_node=routers[router_id])) - link_count += 1 - - # Connect the dir nodes to the corners. - ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0], - int_node=routers[0])) - link_count += 1 - ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[1], - int_node=routers[num_columns - 1])) - link_count += 1 - ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[2], - int_node=routers[num_routers - num_columns])) - link_count += 1 - ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[3], - int_node=routers[num_routers - 1])) - link_count += 1 - - # Connect the dma nodes to router 0. These should only be DMA nodes. - for (i, node) in enumerate(dma_nodes): - assert(node.type == 'DMA_Controller') - ext_links.append(ExtLink(link_id=link_count, ext_node=node, - int_node=routers[0])) - - network.ext_links = ext_links - - # Create the mesh links. First row (east-west) links then column - # (north-south) links - int_links = [] - for row in xrange(num_rows): - for col in xrange(num_columns): - if (col + 1 < num_columns): - east_id = col + (row * num_columns) - west_id = (col + 1) + (row * num_columns) - int_links.append(IntLink(link_id=link_count, - node_a=routers[east_id], - node_b=routers[west_id], - weight=1)) - link_count += 1 - - for col in xrange(num_columns): - for row in xrange(num_rows): - if (row + 1 < num_rows): - north_id = col + (row * num_columns) - south_id = col + ((row + 1) * num_columns) - int_links.append(IntLink(link_id=link_count, - node_a=routers[north_id], - node_b=routers[south_id], - weight=2)) - link_count += 1 - - network.int_links = int_links diff --git a/configs/topologies/MeshDirCorners_XY.py b/configs/topologies/MeshDirCorners_XY.py new file mode 100644 index 000000000..47eb48086 --- /dev/null +++ b/configs/topologies/MeshDirCorners_XY.py @@ -0,0 +1,164 @@ +# Copyright (c) 2010 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Brad Beckmann + +from m5.params import * +from m5.objects import * + +from BaseTopology import SimpleTopology + +# Creates a Mesh topology with 4 directories, one at each corner. +# One L1 (and L2, depending on the protocol) are connected to each router. +# XY routing is enforced (using link weights) to guarantee deadlock freedom. + +class MeshDirCorners_XY(SimpleTopology): + description='MeshDirCorners_XY' + + def __init__(self, controllers): + self.nodes = controllers + + def makeTopology(self, options, network, IntLink, ExtLink, Router): + nodes = self.nodes + + num_routers = options.num_cpus + num_rows = options.mesh_rows + + # First determine which nodes are cache cntrls vs. dirs vs. dma + cache_nodes = [] + dir_nodes = [] + dma_nodes = [] + for node in nodes: + if node.type == 'L1Cache_Controller' or \ + node.type == 'L2Cache_Controller': + cache_nodes.append(node) + elif node.type == 'Directory_Controller': + dir_nodes.append(node) + elif node.type == 'DMA_Controller': + dma_nodes.append(node) + + # Obviously the number or rows must be <= the number of routers + # and evenly divisible. Also the number of caches must be a + # multiple of the number of routers and the number of directories + # must be four. + assert(num_rows <= num_routers) + num_columns = int(num_routers / num_rows) + assert(num_columns * num_rows == num_routers) + caches_per_router, remainder = divmod(len(cache_nodes), num_routers) + assert(remainder == 0) + assert(len(dir_nodes) == 4) + + # Create the routers in the mesh + routers = [Router(router_id=i) for i in range(num_routers)] + network.routers = routers + + # link counter to set unique link ids + link_count = 0 + + # Connect each cache controller to the appropriate router + ext_links = [] + for (i, n) in enumerate(cache_nodes): + cntrl_level, router_id = divmod(i, num_routers) + assert(cntrl_level < caches_per_router) + ext_links.append(ExtLink(link_id=link_count, ext_node=n, + int_node=routers[router_id])) + link_count += 1 + + # Connect the dir nodes to the corners. + ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0], + int_node=routers[0])) + link_count += 1 + ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[1], + int_node=routers[num_columns - 1])) + link_count += 1 + ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[2], + int_node=routers[num_routers - num_columns])) + link_count += 1 + ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[3], + int_node=routers[num_routers - 1])) + link_count += 1 + + # Connect the dma nodes to router 0. These should only be DMA nodes. + for (i, node) in enumerate(dma_nodes): + assert(node.type == 'DMA_Controller') + ext_links.append(ExtLink(link_id=link_count, ext_node=node, + int_node=routers[0])) + + network.ext_links = ext_links + + # Create the mesh links. + int_links = [] + + # East output to West input links (weight = 1) + for row in xrange(num_rows): + for col in xrange(num_columns): + if (col + 1 < num_columns): + east_out = col + (row * num_columns) + west_in = (col + 1) + (row * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[east_out], + dst_node=routers[west_in], + weight=1)) + link_count += 1 + + # West output to East input links (weight = 1) + for row in xrange(num_rows): + for col in xrange(num_columns): + if (col + 1 < num_columns): + east_in = col + (row * num_columns) + west_out = (col + 1) + (row * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[west_out], + dst_node=routers[east_in], + weight=1)) + link_count += 1 + + # North output to South input links (weight = 2) + for col in xrange(num_columns): + for row in xrange(num_rows): + if (row + 1 < num_rows): + north_out = col + (row * num_columns) + south_in = col + ((row + 1) * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[north_out], + dst_node=routers[south_in], + weight=2)) + link_count += 1 + + # South output to North input links (weight = 2) + for col in xrange(num_columns): + for row in xrange(num_rows): + if (row + 1 < num_rows): + north_in = col + (row * num_columns) + south_out = col + ((row + 1) * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[south_out], + dst_node=routers[north_in], + weight=2)) + link_count += 1 + + + network.int_links = int_links diff --git a/configs/topologies/Mesh_XY.py b/configs/topologies/Mesh_XY.py new file mode 100644 index 000000000..adf3ebe49 --- /dev/null +++ b/configs/topologies/Mesh_XY.py @@ -0,0 +1,152 @@ +# Copyright (c) 2010 Advanced Micro Devices, Inc. +# 2016 Georgia Institute of Technology +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Brad Beckmann +# Tushar Krishna + +from m5.params import * +from m5.objects import * + +from BaseTopology import SimpleTopology + +# Creates a generic Mesh assuming an equal number of cache +# and directory controllers. +# XY routing is enforced (using link weights) +# to guarantee deadlock freedom. + +class Mesh_XY(SimpleTopology): + description='Mesh_XY' + + def __init__(self, controllers): + self.nodes = controllers + + # Makes a generic mesh + # assuming an equal number of cache and directory cntrls + + def makeTopology(self, options, network, IntLink, ExtLink, Router): + nodes = self.nodes + + num_routers = options.num_cpus + num_rows = options.mesh_rows + + # There must be an evenly divisible number of cntrls to routers + # Also, obviously the number or rows must be <= the number of routers + cntrls_per_router, remainder = divmod(len(nodes), num_routers) + assert(num_rows <= num_routers) + num_columns = int(num_routers / num_rows) + assert(num_columns * num_rows == num_routers) + + # Create the routers in the mesh + routers = [Router(router_id=i) for i in range(num_routers)] + network.routers = routers + + # link counter to set unique link ids + link_count = 0 + + # Add all but the remainder nodes to the list of nodes to be uniformly + # distributed across the network. + network_nodes = [] + remainder_nodes = [] + for node_index in xrange(len(nodes)): + if node_index < (len(nodes) - remainder): + network_nodes.append(nodes[node_index]) + else: + remainder_nodes.append(nodes[node_index]) + + # Connect each node to the appropriate router + ext_links = [] + for (i, n) in enumerate(network_nodes): + cntrl_level, router_id = divmod(i, num_routers) + assert(cntrl_level < cntrls_per_router) + ext_links.append(ExtLink(link_id=link_count, ext_node=n, + int_node=routers[router_id])) + link_count += 1 + + # Connect the remainding nodes to router 0. These should only be + # DMA nodes. + for (i, node) in enumerate(remainder_nodes): + assert(node.type == 'DMA_Controller') + assert(i < remainder) + ext_links.append(ExtLink(link_id=link_count, ext_node=node, + int_node=routers[0])) + link_count += 1 + + network.ext_links = ext_links + + # Create the mesh links. + int_links = [] + + # East output to West input links (weight = 1) + for row in xrange(num_rows): + for col in xrange(num_columns): + if (col + 1 < num_columns): + east_out = col + (row * num_columns) + west_in = (col + 1) + (row * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[east_out], + dst_node=routers[west_in], + weight=1)) + link_count += 1 + + # West output to East input links (weight = 1) + for row in xrange(num_rows): + for col in xrange(num_columns): + if (col + 1 < num_columns): + east_in = col + (row * num_columns) + west_out = (col + 1) + (row * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[west_out], + dst_node=routers[east_in], + weight=1)) + link_count += 1 + + # North output to South input links (weight = 2) + for col in xrange(num_columns): + for row in xrange(num_rows): + if (row + 1 < num_rows): + north_out = col + (row * num_columns) + south_in = col + ((row + 1) * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[north_out], + dst_node=routers[south_in], + weight=2)) + link_count += 1 + + # South output to North input links (weight = 2) + for col in xrange(num_columns): + for row in xrange(num_rows): + if (row + 1 < num_rows): + north_in = col + (row * num_columns) + south_out = col + ((row + 1) * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[south_out], + dst_node=routers[north_in], + weight=2)) + link_count += 1 + + + network.int_links = int_links diff --git a/configs/topologies/Mesh_westfirst.py b/configs/topologies/Mesh_westfirst.py new file mode 100644 index 000000000..3af894f93 --- /dev/null +++ b/configs/topologies/Mesh_westfirst.py @@ -0,0 +1,158 @@ +# Copyright (c) 2010 Advanced Micro Devices, Inc. +# 2016 Georgia Institute of Technology +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Brad Beckmann +# Tushar Krishna + +from m5.params import * +from m5.objects import * + +from BaseTopology import SimpleTopology + +# Creates a generic Mesh assuming an equal number of cache +# and directory controllers. +# West-first routing is enforced (using link weights) +# to guarantee deadlock freedom. +# The network randomly chooses between links with the same +# weight for messages within unordered virtual networks. +# Within ordered virtual networks, a fixed link direction +# is always chosen based on which appears first inside the +# routing table. + +class Mesh_westfirst(SimpleTopology): + description='Mesh_westfirst' + + def __init__(self, controllers): + self.nodes = controllers + + # Makes a generic mesh + # assuming an equal number of cache and directory cntrls + + def makeTopology(self, options, network, IntLink, ExtLink, Router): + nodes = self.nodes + + num_routers = options.num_cpus + num_rows = options.mesh_rows + + # There must be an evenly divisible number of cntrls to routers + # Also, obviously the number or rows must be <= the number of routers + cntrls_per_router, remainder = divmod(len(nodes), num_routers) + assert(num_rows <= num_routers) + num_columns = int(num_routers / num_rows) + assert(num_columns * num_rows == num_routers) + + # Create the routers in the mesh + routers = [Router(router_id=i) for i in range(num_routers)] + network.routers = routers + + # link counter to set unique link ids + link_count = 0 + + # Add all but the remainder nodes to the list of nodes to be uniformly + # distributed across the network. + network_nodes = [] + remainder_nodes = [] + for node_index in xrange(len(nodes)): + if node_index < (len(nodes) - remainder): + network_nodes.append(nodes[node_index]) + else: + remainder_nodes.append(nodes[node_index]) + + # Connect each node to the appropriate router + ext_links = [] + for (i, n) in enumerate(network_nodes): + cntrl_level, router_id = divmod(i, num_routers) + assert(cntrl_level < cntrls_per_router) + ext_links.append(ExtLink(link_id=link_count, ext_node=n, + int_node=routers[router_id])) + link_count += 1 + + # Connect the remainding nodes to router 0. These should only be + # DMA nodes. + for (i, node) in enumerate(remainder_nodes): + assert(node.type == 'DMA_Controller') + assert(i < remainder) + ext_links.append(ExtLink(link_id=link_count, ext_node=node, + int_node=routers[0])) + link_count += 1 + + network.ext_links = ext_links + + # Create the mesh links. + int_links = [] + + # East output to West input links (weight = 2) + for row in xrange(num_rows): + for col in xrange(num_columns): + if (col + 1 < num_columns): + east_out = col + (row * num_columns) + west_in = (col + 1) + (row * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[east_out], + dst_node=routers[west_in], + weight=2)) + link_count += 1 + + # West output to East input links (weight = 1) + for row in xrange(num_rows): + for col in xrange(num_columns): + if (col + 1 < num_columns): + east_in = col + (row * num_columns) + west_out = (col + 1) + (row * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[west_out], + dst_node=routers[east_in], + weight=1)) + link_count += 1 + + + # North output to South input links (weight = 2) + for col in xrange(num_columns): + for row in xrange(num_rows): + if (row + 1 < num_rows): + north_out = col + (row * num_columns) + south_in = col + ((row + 1) * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[north_out], + dst_node=routers[south_in], + weight=2)) + link_count += 1 + + # South output to North input links (weight = 2) + for col in xrange(num_columns): + for row in xrange(num_rows): + if (row + 1 < num_rows): + north_in = col + (row * num_columns) + south_out = col + ((row + 1) * num_columns) + int_links.append(IntLink(link_id=link_count, + src_node=routers[south_out], + dst_node=routers[north_in], + weight=2)) + link_count += 1 + + + network.int_links = int_links diff --git a/configs/topologies/Pt2Pt.py b/configs/topologies/Pt2Pt.py index 8fada26bf..006d00c2f 100644 --- a/configs/topologies/Pt2Pt.py +++ b/configs/topologies/Pt2Pt.py @@ -57,7 +57,7 @@ class Pt2Pt(SimpleTopology): if (i != j): link_count += 1 int_links.append(IntLink(link_id=link_count, - node_a=routers[i], - node_b=routers[j])) + src_node=routers[i], + dst_node=routers[j])) network.int_links = int_links diff --git a/configs/topologies/Torus.py b/configs/topologies/Torus.py deleted file mode 100644 index db67d3ede..000000000 --- a/configs/topologies/Torus.py +++ /dev/null @@ -1,129 +0,0 @@ -# Copyright (c) 2011 Advanced Micro Devices, Inc. -# 2011 Massachusetts Institute of Technology -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Brad Beckmann -# Tushar Krishna - -from m5.params import * -from m5.objects import * - -from BaseTopology import SimpleTopology - -class Torus(SimpleTopology): - description='Torus' - - def __init__(self, controllers): - self.nodes = controllers - - # Makes a generic torus assuming an equal number of cache and directory cntrls - # Assuming a folded-torus on-chip layout (as shown on gem5 wiki). - # All links (including the wrap-around ones) are of equal length, double that - # of a mesh. Thus, each link is assigned a latency of 2 cycles. - - def makeTopology(self, options, network, IntLink, ExtLink, Router): - nodes = self.nodes - - num_routers = options.num_cpus - num_rows = options.mesh_rows - - # There must be an evenly divisible number of cntrls to routers - # Also, obviously the number or rows must be <= the number of routers - cntrls_per_router, remainder = divmod(len(nodes), num_routers) - assert(num_rows <= num_routers) - num_columns = int(num_routers / num_rows) - assert(num_columns * num_rows == num_routers) - - # Create the routers in the torus - routers = [Router(router_id=i) for i in range(num_routers)] - network.routers = routers - - # link counter to set unique link ids - link_count = 0 - - # Add all but the remainder nodes to the list of nodes to be uniformly - # distributed across the network. - network_nodes = [] - remainder_nodes = [] - for node_index in xrange(len(nodes)): - if node_index < (len(nodes) - remainder): - network_nodes.append(nodes[node_index]) - else: - remainder_nodes.append(nodes[node_index]) - - # Connect each node to the appropriate router - ext_links = [] - for (i, n) in enumerate(network_nodes): - cntrl_level, router_id = divmod(i, num_routers) - assert(cntrl_level < cntrls_per_router) - ext_links.append(ExtLink(link_id=link_count, ext_node=n, - int_node=routers[router_id])) - link_count += 1 - - # Connect the remainding nodes to router 0. These should only be - # DMA nodes. - for (i, node) in enumerate(remainder_nodes): - assert(node.type == 'DMA_Controller') - assert(i < remainder) - ext_links.append(ExtLink(link_id=link_count, ext_node=node, - int_node=routers[0])) - link_count += 1 - - network.ext_links = ext_links - - # Create the torus links. First row (east-west) links then column - # (north-south) links - # column links are given higher weights to implement XY routing - int_links = [] - for row in xrange(num_rows): - for col in xrange(num_columns): - west_id = col + (row * num_columns) - if (col + 1 < num_columns): - east_id = (col + 1) + (row * num_columns) - else: - east_id = (row * num_columns) - int_links.append(IntLink(link_id=link_count, - node_a=routers[east_id], - node_b=routers[west_id], - latency=2, - weight=1)) - link_count += 1 - - for col in xrange(num_columns): - for row in xrange(num_rows): - north_id = col + (row * num_columns) - if (row + 1 < num_rows): - south_id = col + ((row + 1) * num_columns) - else: - south_id = col - int_links.append(IntLink(link_id=link_count, - node_a=routers[north_id], - node_b=routers[south_id], - latency=2, - weight=2)) - link_count += 1 - - network.int_links = int_links diff --git a/src/mem/ruby/network/BasicLink.cc b/src/mem/ruby/network/BasicLink.cc index 292e74e96..2b55e7ec8 100644 --- a/src/mem/ruby/network/BasicLink.cc +++ b/src/mem/ruby/network/BasicLink.cc @@ -56,8 +56,6 @@ BasicLinkParams::create() BasicExtLink::BasicExtLink(const Params *p) : BasicLink(p) { - m_int_node = p->int_node; - m_ext_node = p->ext_node; } BasicExtLink * @@ -69,8 +67,6 @@ BasicExtLinkParams::create() BasicIntLink::BasicIntLink(const Params *p) : BasicLink(p) { - m_node_a = p->node_a; - m_node_b = p->node_b; } BasicIntLink * diff --git a/src/mem/ruby/network/BasicLink.hh b/src/mem/ruby/network/BasicLink.hh index 634b9143e..188f62941 100644 --- a/src/mem/ruby/network/BasicLink.hh +++ b/src/mem/ruby/network/BasicLink.hh @@ -73,10 +73,6 @@ class BasicExtLink : public BasicLink const Params *params() const { return (const Params *)_params; } friend class Topology; - - protected: - BasicRouter* m_int_node; - AbstractController* m_ext_node; }; class BasicIntLink : public BasicLink @@ -87,10 +83,6 @@ class BasicIntLink : public BasicLink const Params *params() const { return (const Params *)_params; } friend class Topology; - - protected: - BasicRouter* m_node_a; - BasicRouter* m_node_b; }; #endif // __MEM_RUBY_NETWORK_BASIC_LINK_HH__ diff --git a/src/mem/ruby/network/BasicLink.py b/src/mem/ruby/network/BasicLink.py index 8fc83c9e2..5da5dc6a2 100644 --- a/src/mem/ruby/network/BasicLink.py +++ b/src/mem/ruby/network/BasicLink.py @@ -35,10 +35,9 @@ class BasicLink(SimObject): cxx_header = "mem/ruby/network/BasicLink.hh" link_id = Param.Int("ID in relation to other links") latency = Param.Cycles(1, "latency") - # The following banwidth factor does not translate to the same value for - # both the simple and Garnet models. For the most part, the bandwidth - # factor is the width of the link in bytes, expect for certain situations - # with regard to the simple network. + # Width of the link in bytes + # Only used by simple network. + # Garnet models this by flit size bandwidth_factor = Param.Int("generic bandwidth factor, usually in bytes") weight = Param.Int(1, "used to restrict routing in shortest path analysis") @@ -52,6 +51,6 @@ class BasicExtLink(BasicLink): class BasicIntLink(BasicLink): type = 'BasicIntLink' cxx_header = "mem/ruby/network/BasicLink.hh" - node_a = Param.BasicRouter("Router on one end") - node_b = Param.BasicRouter("Router on other end") + src_node = Param.BasicRouter("Router on src end") + dst_node = Param.BasicRouter("Router on dst end") bandwidth_factor = 16 diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh index c06ee5a1a..529408696 100644 --- a/src/mem/ruby/network/Network.hh +++ b/src/mem/ruby/network/Network.hh @@ -80,14 +80,11 @@ class Network : public ClockedObject virtual void checkNetworkAllocation(NodeID id, bool ordered, int network_num, std::string vnet_type); - virtual void makeOutLink(SwitchID src, NodeID dest, BasicLink* link, - LinkDirection direction, + virtual void makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link, const NetDest& routing_table_entry) = 0; - virtual void makeInLink(NodeID src, SwitchID dest, BasicLink* link, - LinkDirection direction, + virtual void makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, const NetDest& routing_table_entry) = 0; virtual void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, - LinkDirection direction, const NetDest& routing_table_entry) = 0; virtual void collateStats() = 0; diff --git a/src/mem/ruby/network/Topology.cc b/src/mem/ruby/network/Topology.cc index 757efe063..f73e686c5 100644 --- a/src/mem/ruby/network/Topology.cc +++ b/src/mem/ruby/network/Topology.cc @@ -55,10 +55,14 @@ Topology::Topology(uint32_t num_routers, // Total nodes/controllers in network assert(m_nodes > 1); - // analyze both the internal and external links, create data structures - // Note that the python created links are bi-directional, but that the - // topology and networks utilize uni-directional links. Thus each - // BasicLink is converted to two calls to add link, on for each direction + // analyze both the internal and external links, create data structures. + // The python created external links are bi-directional, + // and the python created internal links are uni-directional. + // The networks and topology utilize uni-directional links. + // Thus each external link is converted to two calls to addLink, + // one for each direction. + // + // External Links for (vector::const_iterator i = ext_links.begin(); i != ext_links.end(); ++i) { BasicExtLink *ext_link = (*i); @@ -71,29 +75,27 @@ Topology::Topology(uint32_t num_routers, int int_idx = router->params()->router_id + 2*m_nodes; // create the internal uni-directional links in both directions - // the first direction is marked: In - addLink(ext_idx1, int_idx, ext_link, LinkDirection_In); - // the first direction is marked: Out - addLink(int_idx, ext_idx2, ext_link, LinkDirection_Out); + // ext to int + addLink(ext_idx1, int_idx, ext_link); + // int to ext + addLink(int_idx, ext_idx2, ext_link); } + // Internal Links for (vector::const_iterator i = int_links.begin(); i != int_links.end(); ++i) { BasicIntLink *int_link = (*i); - BasicRouter *router_a = int_link->params()->node_a; - BasicRouter *router_b = int_link->params()->node_b; + BasicRouter *router_src = int_link->params()->src_node; + BasicRouter *router_dst = int_link->params()->dst_node; // Store the IntLink pointers for later m_int_link_vector.push_back(int_link); - int a = router_a->params()->router_id + 2*m_nodes; - int b = router_b->params()->router_id + 2*m_nodes; + int src = router_src->params()->router_id + 2*m_nodes; + int dst = router_dst->params()->router_id + 2*m_nodes; - // create the internal uni-directional links in both directions - // the first direction is marked: In - addLink(a, b, int_link, LinkDirection_In); - // the second direction is marked: Out - addLink(b, a, int_link, LinkDirection_Out); + // create the internal uni-directional link from src to dst + addLink(src, dst, int_link); } } @@ -151,8 +153,7 @@ Topology::createLinks(Network *net) } void -Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link, - LinkDirection dir) +Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link) { assert(src <= m_number_of_switches+m_nodes+m_nodes); assert(dest <= m_number_of_switches+m_nodes+m_nodes); @@ -162,7 +163,6 @@ Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link, src_dest_pair.first = src; src_dest_pair.second = dest; - link_entry.direction = dir; link_entry.link = link; m_link_map[src_dest_pair] = link_entry; } @@ -182,23 +182,23 @@ Topology::makeLink(Network *net, SwitchID src, SwitchID dest, src_dest.first = src; src_dest.second = dest; link_entry = m_link_map[src_dest]; - net->makeInLink(src, dest - (2 * m_nodes), link_entry.link, - link_entry.direction, routing_table_entry); + net->makeExtInLink(src, dest - (2 * m_nodes), link_entry.link, + routing_table_entry); } else if (dest < 2*m_nodes) { assert(dest >= m_nodes); NodeID node = dest - m_nodes; src_dest.first = src; src_dest.second = dest; link_entry = m_link_map[src_dest]; - net->makeOutLink(src - (2 * m_nodes), node, link_entry.link, - link_entry.direction, routing_table_entry); + net->makeExtOutLink(src - (2 * m_nodes), node, link_entry.link, + routing_table_entry); } else { assert((src >= 2 * m_nodes) && (dest >= 2 * m_nodes)); src_dest.first = src; src_dest.second = dest; link_entry = m_link_map[src_dest]; net->makeInternalLink(src - (2 * m_nodes), dest - (2 * m_nodes), - link_entry.link, link_entry.direction, + link_entry.link, routing_table_entry); } } diff --git a/src/mem/ruby/network/Topology.hh b/src/mem/ruby/network/Topology.hh index d55ba99a9..7e0b12c63 100644 --- a/src/mem/ruby/network/Topology.hh +++ b/src/mem/ruby/network/Topology.hh @@ -72,8 +72,7 @@ class Topology void print(std::ostream& out) const { out << "[Topology]"; } private: - void addLink(SwitchID src, SwitchID dest, BasicLink* link, - LinkDirection dir); + void addLink(SwitchID src, SwitchID dest, BasicLink* link); void makeLink(Network *net, SwitchID src, SwitchID dest, const NetDest& routing_table_entry); diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc index ce919335e..1e36a4cf0 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc @@ -127,15 +127,14 @@ GarnetNetwork_d::~GarnetNetwork_d() */ void -GarnetNetwork_d::makeInLink(NodeID src, SwitchID dest, BasicLink* link, - LinkDirection direction, +GarnetNetwork_d::makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, const NetDest& routing_table_entry) { assert(src < m_nodes); GarnetExtLink_d* garnet_link = safe_cast(link); - NetworkLink_d* net_link = garnet_link->m_network_links[direction]; - CreditLink_d* credit_link = garnet_link->m_credit_links[direction]; + NetworkLink_d* net_link = garnet_link->m_network_links[0]; + CreditLink_d* credit_link = garnet_link->m_credit_links[0]; m_links.push_back(net_link); m_creditlinks.push_back(credit_link); @@ -151,8 +150,7 @@ GarnetNetwork_d::makeInLink(NodeID src, SwitchID dest, BasicLink* link, */ void -GarnetNetwork_d::makeOutLink(SwitchID src, NodeID dest, BasicLink* link, - LinkDirection direction, +GarnetNetwork_d::makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link, const NetDest& routing_table_entry) { assert(dest < m_nodes); @@ -160,8 +158,8 @@ GarnetNetwork_d::makeOutLink(SwitchID src, NodeID dest, BasicLink* link, assert(m_routers[src] != NULL); GarnetExtLink_d* garnet_link = safe_cast(link); - NetworkLink_d* net_link = garnet_link->m_network_links[direction]; - CreditLink_d* credit_link = garnet_link->m_credit_links[direction]; + NetworkLink_d* net_link = garnet_link->m_network_links[1]; + CreditLink_d* credit_link = garnet_link->m_credit_links[1]; m_links.push_back(net_link); m_creditlinks.push_back(credit_link); @@ -177,12 +175,11 @@ GarnetNetwork_d::makeOutLink(SwitchID src, NodeID dest, BasicLink* link, void GarnetNetwork_d::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, - LinkDirection direction, const NetDest& routing_table_entry) { GarnetIntLink_d* garnet_link = safe_cast(link); - NetworkLink_d* net_link = garnet_link->m_network_links[direction]; - CreditLink_d* credit_link = garnet_link->m_credit_links[direction]; + NetworkLink_d* net_link = garnet_link->m_network_links[0]; + CreditLink_d* credit_link = garnet_link->m_credit_links[0]; m_links.push_back(net_link); m_creditlinks.push_back(credit_link); diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh index 99ecc02da..a11f3ea50 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh @@ -69,14 +69,11 @@ class GarnetNetwork_d : public BaseGarnetNetwork } // Methods used by Topology to setup the network - void makeOutLink(SwitchID src, NodeID dest, BasicLink* link, - LinkDirection direction, + void makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link, const NetDest& routing_table_entry); - void makeInLink(NodeID src, SwitchID dest, BasicLink* link, - LinkDirection direction, + void makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, const NetDest& routing_table_entry); void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, - LinkDirection direction, const NetDest& routing_table_entry); //! Function for performing a functional write. The return value diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc index bd96fc2ed..0b33ab009 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc @@ -94,14 +94,13 @@ GarnetNetwork::~GarnetNetwork() } void -GarnetNetwork::makeInLink(NodeID src, SwitchID dest, BasicLink* link, - LinkDirection direction, +GarnetNetwork::makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, const NetDest& routing_table_entry) { assert(src < m_nodes); GarnetExtLink* garnet_link = safe_cast(link); - NetworkLink *net_link = garnet_link->m_network_links[direction]; + NetworkLink *net_link = garnet_link->m_network_links[0]; net_link->init_net_ptr(this); m_links.push_back(net_link); @@ -110,8 +109,7 @@ GarnetNetwork::makeInLink(NodeID src, SwitchID dest, BasicLink* link, } void -GarnetNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link, - LinkDirection direction, +GarnetNetwork::makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link, const NetDest& routing_table_entry) { assert(dest < m_nodes); @@ -119,7 +117,7 @@ GarnetNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link, assert(m_routers[src] != NULL); GarnetExtLink* garnet_link = safe_cast(link); - NetworkLink *net_link = garnet_link->m_network_links[direction]; + NetworkLink *net_link = garnet_link->m_network_links[1]; net_link->init_net_ptr(this); m_links.push_back(net_link); @@ -130,11 +128,10 @@ GarnetNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link, void GarnetNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, - LinkDirection direction, const NetDest& routing_table_entry) { GarnetIntLink* garnet_link = safe_cast(link); - NetworkLink *net_link = garnet_link->m_network_links[direction]; + NetworkLink *net_link = garnet_link->m_network_links[0]; net_link->init_net_ptr(this); m_links.push_back(net_link); diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh index e9b94809f..18360d475 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh @@ -60,14 +60,11 @@ class GarnetNetwork : public BaseGarnetNetwork void print(std::ostream& out) const; // Methods used by Topology to setup the network - void makeOutLink(SwitchID src, NodeID dest, BasicLink* link, - LinkDirection direction, + void makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link, const NetDest& routing_table_entry); - void makeInLink(NodeID src, SwitchID dest, BasicLink* link, - LinkDirection direction, + void makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, const NetDest& routing_table_entry); void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, - LinkDirection direction, const NetDest& routing_table_entry); //! Function for performing a functional read. The return value diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc index 2fc7b6440..b30bd8731 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.cc +++ b/src/mem/ruby/network/simple/SimpleNetwork.cc @@ -78,8 +78,7 @@ SimpleNetwork::~SimpleNetwork() // From a switch to an endpoint node void -SimpleNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link, - LinkDirection direction, +SimpleNetwork::makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link, const NetDest& routing_table_entry) { assert(dest < m_nodes); @@ -95,8 +94,7 @@ SimpleNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link, // From an endpoint node to a switch void -SimpleNetwork::makeInLink(NodeID src, SwitchID dest, BasicLink* link, - LinkDirection direction, +SimpleNetwork::makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, const NetDest& routing_table_entry) { assert(src < m_nodes); @@ -106,7 +104,6 @@ SimpleNetwork::makeInLink(NodeID src, SwitchID dest, BasicLink* link, // From a switch to a switch void SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, - LinkDirection direction, const NetDest& routing_table_entry) { // Create a set of new MessageBuffers diff --git a/src/mem/ruby/network/simple/SimpleNetwork.hh b/src/mem/ruby/network/simple/SimpleNetwork.hh index 434dfa702..6a325d2a4 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.hh +++ b/src/mem/ruby/network/simple/SimpleNetwork.hh @@ -59,14 +59,11 @@ class SimpleNetwork : public Network bool isVNetOrdered(int vnet) const { return m_ordered[vnet]; } // Methods used by Topology to setup the network - void makeOutLink(SwitchID src, NodeID dest, BasicLink* link, - LinkDirection direction, + void makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link, const NetDest& routing_table_entry); - void makeInLink(NodeID src, SwitchID dest, BasicLink* link, - LinkDirection direction, + void makeExtInLink(NodeID src, SwitchID dest, BasicLink* link, const NetDest& routing_table_entry); void makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, - LinkDirection direction, const NetDest& routing_table_entry); void print(std::ostream& out) const; diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py b/src/mem/ruby/network/simple/SimpleNetwork.py index 87de0fb46..3d6f7e854 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.py +++ b/src/mem/ruby/network/simple/SimpleNetwork.py @@ -56,12 +56,10 @@ class SimpleNetwork(RubyNetwork): # Also add buffers for all router-link connections for router in self.routers: router_buffers = [] - # Add message buffers to routers for each internal link connection + # Add message buffers to routers at the end of each + # unidirectional internal link for link in self.int_links: - if link.node_a == router: - for i in xrange(self.number_of_virtual_networks): - router_buffers.append(MessageBuffer(ordered = True)) - if link.node_b == router: + if link.dst_node == router: for i in xrange(self.number_of_virtual_networks): router_buffers.append(MessageBuffer(ordered = True))