From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 25 Sep 2021 19:20:24 +0000 (+0100)
Subject: comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=006a05dbea6682535341b8d6be5627f2733d3ead;p=soc.git

comments
---

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index e4e109ec..32c19db5 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -381,6 +381,8 @@ class TestRunner(FHDLTestCase):
             simrun = SimRunner(self, m, pspec)
 
         # run core clock at same rate as test clock
+        # XXX this has to stay here! TODO, work out why,
+        # but Simulation-only fails without it
         intclk = ClockSignal("coresync")
         comb += intclk.eq(ClockSignal())