From: lkcl <lkcl@web>
Date: Sun, 8 May 2022 19:44:28 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2299
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=006ffaeb5966c48aa040b3697ae2a78426826aef;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 69237ee8f..0acb474d5 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -846,7 +846,9 @@ traditional CPU in no way can help: only by loading the data through
 the L1-L4 Cache and Virtual Memory Barriers is it possible to
 ascertain, retrospectively, that time and power had just been wasted.
 
-SVP64 is able to do what is termed "Vertical-First" Vectorisation,
+SVP64 is able to do what is termed "Vertical-First" Vectorisation
+*(walk first through a batch of instructions before explicitly
+moving to the next element, and repeating the batch)*,
 combined with SVREMAP Matrix Schedules.  Imagine that SVREMAP has been
 extended, Snitch-style, to perform a deterministic memory-array walk of
 a large Matrix.