From: lkcl <lkcl@web>
Date: Fri, 29 Jan 2021 14:10:28 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~247
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0073db2712a98e214d7d860be1f6e26772048ccf;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 25f0f949e..e60c5bb85 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -122,3 +122,15 @@ Due to the need for exceptions to occur in the middle, the loop should *not* be
 * power-gem5: TODO
 * TestIssuer: TODO
 * Microwatt: TODO
+
+## Increasing register file sizes
+
+TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
+
+## Single Predication
+
+TODO
+
+## Element width overrides
+
+TODO