From: lkcl <lkcl@web>
Date: Tue, 15 Feb 2022 06:34:28 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3203
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0078f2a1d3185fb2d00da369ff6f6f42025c9523;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index a3248d830..5cb5d51f3 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -318,6 +318,11 @@ uint_xlen_t bmextrev(RA, RB, sh)
 
 # grevlut
 
+generalised reverse combined with a LUT2 and allowing
+zero when RA=0 provides a wide range of instructions
+and a means to set regular 64 bit patterns in one
+32 bit instruction.
+
 ```
 lut2(imm, a, b):
     idx = b << 1 | a