From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 May 2020 16:20:53 +0000 (+0100)
Subject: idea: invert pos/neg test in output stage, uses an XOR instead of QTY 2 64-bit
X-Git-Tag: div_pipeline~1232
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=007b865eb97e970a9b7f7fc6bf06adf5b70ec707;p=soc.git

idea: invert pos/neg test in output stage, uses an XOR instead of QTY 2 64-bit
MUXes and a mess/morass of code
---

diff --git a/libreriscv b/libreriscv
index ad0436ee..eda9879f 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit ad0436eed1fcf36e0f1acfde5de71ad2e4b56145
+Subproject commit eda9879fef1cddcd9fb41fca982a6b86e471905b
diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py
index f5a50160..5de9bbd0 100644
--- a/src/soc/alu/output_stage.py
+++ b/src/soc/alu/output_stage.py
@@ -33,8 +33,12 @@ class ALUOutputStage(PipeModBase):
         is_zero = Signal(reset_less=True)
         is_positive = Signal(reset_less=True)
         is_negative = Signal(reset_less=True)
+        msb_test = Signal(reset_less=True) # set equal to MSB, invert if OP=CMP
         so = Signal(reset_less=True)
 
+        # TODO: if o[63] is XORed with "operand == OP_CMP"
+        # that can be used as a test
+        # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
         comb += is_zero.eq(o == 0)
         comb += is_positive.eq(~is_zero & ~o[63])
         comb += is_negative.eq(~is_zero & o[63])